Difference between revisions of "High Performance SoCs"
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==Contact Information== | ==Contact Information== | ||
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===[[:User:Paulsc | Paul Scheffler]]=== | ===[[:User:Paulsc | Paul Scheffler]]=== | ||
* '''e-mail''': [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch] | * '''e-mail''': [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch] | ||
* '''phone''': +41 44 632 09 15 | * '''phone''': +41 44 632 09 15 | ||
* '''office''': ETZ J85 | * '''office''': ETZ J85 | ||
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===[[:User:Tbenz | Thomas Benz]]=== | ===[[:User:Tbenz | Thomas Benz]]=== | ||
Revision as of 16:01, 20 October 2020
Contents
Contact Information
 |
Paul Scheffler
|
Thomas Benz
- e-mail: tbenz@iis.ee.ethz.ch
- phone: +41 44 632 05 18
- office: ETZ J85
Nils Wistoff
- e-mail: nwistoff@iis.ee.ethz.ch
- phone: +41 44 632 06 75
- office: ETZ J85
Projects
Available Projects
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Hypervisor Extension for Ariane (M)
- RISC-V base ISA for ultra-low-area cores (2-3G)
- IP-Based SoC Generation and Configuration (1-3S/B)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
Projects In Progress
- ISA extensions in the Snitch Processor for Signal Processing (M)
- MemPool on HERO (1S)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
