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Showing below up to 100 results in range #401 to #500.

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  1. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers‏‎ (11:08, 12 November 2020)
  2. Low-Resolution 5G Beamforming Codebook Design‏‎ (11:37, 12 November 2020)
  3. Real-Time Optimization‏‎ (13:57, 12 November 2020)
  4. Deep Unfolding of Iterative Optimization Algorithms‏‎ (13:57, 12 November 2020)
  5. LightProbe - CNN-Based-Image-Reconstruction‏‎ (20:46, 12 November 2020)
  6. LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)‏‎ (20:47, 12 November 2020)
  7. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)‏‎ (20:48, 12 November 2020)
  8. Ultrasound High Speed Microbubble Tracking‏‎ (20:49, 12 November 2020)
  9. LightProbe - Thermal-Power aware on-head Beamforming‏‎ (20:50, 12 November 2020)
  10. LightProbe - Frontend Firmware and Control Side Channel‏‎ (20:51, 12 November 2020)
  11. 3D Ultrasound Bubble Tracking‏‎ (20:52, 12 November 2020)
  12. Satellite Internet of Things‏‎ (13:53, 13 November 2020)
  13. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things‏‎ (13:54, 13 November 2020)
  14. Next Generation Channel Decoder‏‎ (14:01, 13 November 2020)
  15. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications‏‎ (15:31, 16 November 2020)
  16. FFT HDL Code Generator for Multi-Antenna mmWave Communication‏‎ (19:40, 16 November 2020)
  17. Autonomus Drones With Novel Sensors And Ultra Wide Band‏‎ (11:39, 30 November 2020)
  18. Smart Patch For Heath Care And Rehabilitation‏‎ (16:24, 30 November 2020)
  19. Matheus Cavalcante‏‎ (18:33, 8 December 2020)
  20. Improved Reacquisition for the 5G Cellular IoT‏‎ (14:04, 11 January 2021)
  21. ASIC Design of a Gaussian Message Passing Processor‏‎ (08:34, 20 January 2021)
  22. ASIC Design of a Sigma Point Processor‏‎ (08:34, 20 January 2021)
  23. Hardware Accelerator for Model Predictive Controller‏‎ (08:35, 20 January 2021)
  24. Fast Wakeup From Deep Sleep State‏‎ (08:35, 20 January 2021)
  25. Compressed Sensing for Wireless Biosignal Monitoring‏‎ (08:35, 20 January 2021)
  26. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP‏‎ (08:36, 20 January 2021)
  27. Autoencoder Accelerator for On-Chip Semi-Supervised Learning‏‎ (08:37, 20 January 2021)
  28. Extend the RI5CY core with priviledge extensions‏‎ (08:38, 20 January 2021)
  29. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core‏‎ (08:42, 20 January 2021)
  30. MemPool on HERO (1S)‏‎ (19:07, 20 January 2021)
  31. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (19:05, 29 January 2021)
  32. Resilient Brain-Inspired Hyperdimensional Computing Architectures‏‎ (19:08, 29 January 2021)
  33. Level Crossing ADC For a Many Channels Neural Recording Interface‏‎ (19:10, 29 January 2021)
  34. RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB‏‎ (19:10, 29 January 2021)
  35. Spiking Neural Network for Autonomous Navigation‏‎ (19:10, 29 January 2021)
  36. Event-Driven Convolutional Neural Network Modular Accelerator‏‎ (19:10, 29 January 2021)
  37. ASIC Design Projects‏‎ (19:13, 29 January 2021)
  38. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core‏‎ (19:19, 29 January 2021)
  39. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (23:59, 6 February 2021)
  40. Heroino: Design of the next CORE-V Microcontroller‏‎ (00:01, 7 February 2021)
  41. VLSI Implementation of a 5G Ciphering Accelerator‏‎ (10:05, 9 February 2021)
  42. OTDOA Positioning for LTE Cat-M‏‎ (15:50, 9 February 2021)
  43. ASIC Development of 5G-NR LDPC Decoder‏‎ (01:43, 10 February 2021)
  44. Wireless Communication Systems for the IoT‏‎ (01:45, 10 February 2021)
  45. Software-Defined Paging in the Snitch Cluster (2-3S)‏‎ (20:08, 15 February 2021)
  46. Event-Driven Vision on an embedded platform‏‎ (08:41, 17 February 2021)
  47. Efficient TNN compression‏‎ (08:41, 17 February 2021)
  48. Design and Evaluation of a Small Size Avalanche Beacon‏‎ (10:02, 22 February 2021)
  49. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (00:08, 13 March 2021)
  50. A Flexible Peripheral System for High-Performance Systems on Chip (M)‏‎ (15:40, 15 March 2021)
  51. Stand-Alone Edge Computing with GAP8‏‎ (14:38, 14 April 2021)
  52. Neural Networks Framwork for Embedded Plattforms‏‎ (14:40, 14 April 2021)
  53. Ibex: Tightly-Coupled Accelerators and ISA Extensions‏‎ (12:52, 27 April 2021)
  54. Intelligent Power Management Unit (iPMU)‏‎ (11:40, 2 June 2021)
  55. PULP in space - Fault Tolerant PULP System for Critical Space Applications‏‎ (14:46, 2 June 2021)
  56. Andreas Kurth‏‎ (07:40, 11 June 2021)
  57. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)‏‎ (12:21, 23 June 2021)
  58. Integrated silicon photonic structures-Lumiphase‏‎ (13:53, 23 June 2021)
  59. Integrated silicon photonic structures‏‎ (13:58, 23 June 2021)
  60. Phase-change memory devices for emerging computing paradigms‏‎ (14:13, 23 June 2021)
  61. Finite Element Simulations of Transistors for Quantum Computing‏‎ (14:14, 23 June 2021)
  62. Manycore System on FPGA (M/S/G)‏‎ (10:41, 6 July 2021)
  63. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (10:41, 6 July 2021)
  64. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)‏‎ (15:18, 9 July 2021)
  65. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)‏‎ (15:18, 9 July 2021)
  66. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)‏‎ (15:19, 9 July 2021)
  67. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)‏‎ (15:19, 9 July 2021)
  68. LLVM and DaCe for Snitch (1-2S)‏‎ (15:20, 9 July 2021)
  69. Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)‏‎ (15:21, 9 July 2021)
  70. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)‏‎ (15:21, 9 July 2021)
  71. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (15:25, 9 July 2021)
  72. Unconventional phase change memory device concepts for in-memory and neuromorphic computin‏‎ (13:07, 23 July 2021)
  73. Test page‏‎ (12:30, 27 July 2021)
  74. Semi-Custom Digital VLSI for Processing-in-Memory‏‎ (14:33, 28 July 2021)
  75. SystemVerilog formatter for our LowRISC-based guidelines (2-3G)‏‎ (19:57, 29 July 2021)
  76. Fast Simulation of Manycore Systems (1S)‏‎ (17:20, 2 August 2021)
  77. Evaluating memory access pattern specializations in OoO, server-grade cores (M)‏‎ (13:25, 10 August 2021)
  78. DC-DC Buck converter in 65nm CMOS‏‎ (11:36, 20 August 2021)
  79. Low-Dropout Regulators for Magnetic Resonance Imaging‏‎ (11:38, 20 August 2021)
  80. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging‏‎ (11:40, 20 August 2021)
  81. Ultra-low power transceiver for implantable devices‏‎ (11:43, 20 August 2021)
  82. Inductive Charging Circuit for Implantable Devices‏‎ (11:43, 20 August 2021)
  83. Design of a 25 Gbps SerDes for optical chip-to-chip communication‏‎ (11:44, 20 August 2021)
  84. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT‏‎ (11:45, 20 August 2021)
  85. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT‏‎ (11:45, 20 August 2021)
  86. Design of Charge-Pump PLL in 22nm for 5G communication applications‏‎ (15:51, 20 August 2021)
  87. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)‏‎ (10:54, 31 August 2021)
  88. Bluetooth Low Energy network with optimized data throughput‏‎ (17:18, 14 September 2021)
  89. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications‏‎ (15:31, 15 September 2021)
  90. 5G Cellular RF Front-end Design in 22nm CMOS Technology‏‎ (15:36, 15 September 2021)
  91. Analog building blocks for mmWave manipulation‏‎ (15:44, 15 September 2021)
  92. Low Latency Brain-Machine Interfaces‏‎ (09:18, 16 September 2021)
  93. Hyper-Dimensional Computing Based Predictive Maintenance‏‎ (09:18, 16 September 2021)
  94. Towards global Brain-Computer Interfaces‏‎ (09:20, 16 September 2021)
  95. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation‏‎ (09:23, 16 September 2021)
  96. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control‏‎ (09:25, 16 September 2021)
  97. Every individual on the planet should have a real chance to obtain personalized medical therapy‏‎ (17:04, 16 September 2021)
  98. Characterization techniques for silicon photonics-Lumiphase‏‎ (17:05, 16 September 2021)
  99. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials‏‎ (17:06, 16 September 2021)
  100. Electrothermal characterization of van der Waals Heterostructures with a partial overlap‏‎ (17:06, 16 September 2021)

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