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Showing below up to 100 results in range #251 to #350.
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- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Efficient SoCs
- Engineering For Kids
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Event-based navigation on autonomous nano-drones
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- FFT-based Convolutional Network Accelerator
- FFT HDL Code Generator for Multi-Antenna mmWave Communication
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
- FPGA mapping of RPC DRAM
- Fast Accelerator Context Switch for PULP
- Fast Simulation of Manycore Systems (1S)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Finite Element Simulations of Transistors for Quantum Computing
- Finite element modeling of electrochemical random access memory
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- Forward error-correction ASIC using GRAND
- Freedom from Interference in Heterogeneous COTS SoCs
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- GPT on the edge
- GRAND Hardware Implementation
- GSM Voice Capacity Evolution - VAMOS
- GUI-developement for an action-cam-based eye tracking device
- Glitches Reduce Listening Time of Your iPod
- Gomeza old project1
- Gomeza old project2
- Gomeza old project3
- Gomeza old project4
- Gomeza old project5
- Graph neural networks for epileptic seizure detection
- HERO: TLB Invalidation
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Hardware Accelerated Derivative Pricing
- Hardware Accelerator Integration into Embedded Linux
- Hardware Accelerator for Model Predictive Controller
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Herschmi
- High-Resolution, Calibrated Folding ADCs
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- High-speed Scene Labeling on FPGA
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High Performance Cellular Receivers in Very Advanced CMOS
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hypervisor Extension for Ariane (M)
