Pages with the most revisions
From iis-projects
Showing below up to 50 results in range #251 to #300.
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- A Multiview Synthesis Core in 65 nm CMOS (9 revisions)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (9 revisions)
- Automatic unplugging detection for Ultrasound probes (9 revisions)
- DC-DC Buck converter in 65nm CMOS (9 revisions)
- Configurable Ultra Low Power LDO (9 revisions)
- Gomeza old project2 (9 revisions)
- Energy Efficient SoCs (9 revisions)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (9 revisions)
- Freedom from Interference in Heterogeneous COTS SoCs (9 revisions)
- Improved State Estimation on PULP-based Nano-UAVs (9 revisions)
- Practical Reconfigurable Intelligent Surfaces (RIS) (9 revisions)
- Michael Rogenmoser (9 revisions)
- Hardware Accelerated Derivative Pricing (9 revisions)
- OpenRISC SoC for Sensor Applications (9 revisions)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (9 revisions)
- Real-time View Synthesis using Image Domain Warping (9 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Weekly Reports (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- NVDLA meets PULP (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- Sandro Belfanti (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Pirmin Vogel (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
