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Showing below up to 50 results in range #31 to #80.
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- Probabilistic training algorithms for quantized neural networks (30 revisions)
- Analog (30 revisions)
- ASIC Development of 5G-NR LDPC Decoder (29 revisions)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B) (29 revisions)
- Design of Scalable Event-driven Neural-Recording Digital Interface (29 revisions)
- Energy Efficient Serial Link (28 revisions)
- Probing the limits of fake-quantised neural networks (27 revisions)
- Real-Time Embedded Systems (27 revisions)
- Exploring schedules for incremental and annealing quantization algorithms (26 revisions)
- Skin coupling media characterization for fitnesstracker applications (1 B/S) (25 revisions)
- Smart Meters (24 revisions)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) (24 revisions)
- Open Source Baseband Firmware for 2G Cellular Networks (24 revisions)
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design (24 revisions)
- Ultra-wideband Concurrent Ranging (24 revisions)
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE (23 revisions)
- Real-Time Stereo to Multiview Conversion (22 revisions)
- Low-Dropout Regulators for Magnetic Resonance Imaging (21 revisions)
- Benjamin Weber (21 revisions)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (21 revisions)
- Accelerator for Spatio-Temporal Video Filtering (20 revisions)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration (20 revisions)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (20 revisions)
- Accelerator for Boosted Binary Features (20 revisions)
- 4th Generation Synchronization (19 revisions)
- PULP’s CLIC extensions for fast interrupt handling (19 revisions)
- Wireless Communication Systems for the IoT (19 revisions)
- Trace Debugger for custom RISC-V Core (19 revisions)
- FFT-based Convolutional Network Accelerator (19 revisions)
- Low-Power Environmental Sensing (18 revisions)
- Model Complexity of Electromagnetic Systems (18 revisions)
- Mapping Networks on Reconfigurable Binary Engine Accelerator (18 revisions)
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE (18 revisions)
- Flexfloat DL Training Framework (18 revisions)
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders (18 revisions)
- Improving Scene Labeling with Hyperspectral Data (18 revisions)
- David J. Mack (18 revisions)
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs (17 revisions)
- Energy Efficient Circuits and IoT Systems Group (17 revisions)
- BLISS - Battery-Less Identification System for Security (17 revisions)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (17 revisions)
- Baseband Meets CPU (17 revisions)
- Compressed Sensing vs JPEG (17 revisions)
- Energy Efficient AXI Interface to Serial Link Physical Layer (17 revisions)
- A Snitch-based Compute Accelerator for HERO (17 revisions)
- Fast Accelerator Context Switch for PULP (17 revisions)
- Optimal System Duty Cycling for a Mobile Health Platform (16 revisions)
- LightProbe (16 revisions)
- Rethinking our Convolutional Network Accelerator Architecture (16 revisions)
- 3D Turbo Decoder ASIC Realization (16 revisions)