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Showing below up to 50 results in range #521 to #570.
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- Change-based Evaluation of Convolutional Neural Networks (6 revisions)
- FPGA mapping of RPC DRAM (6 revisions)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (6 revisions)
- Beat Cadence (6 revisions)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (6 revisions)
- Autonomous Smart Watches: Hardware and Software Desing (6 revisions)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (6 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Putting Together What Fits Together - GrÆStl (7 revisions)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Predictable Execution (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- EEG earbud (7 revisions)
- IoT Turbo Decoder (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- Internet of Things Network Synchronizer (7 revisions)
- Fault Tolerance (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- Outdoor Precision Object Tracking for Rockfall Experiments (7 revisions)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (7 revisions)
- Gomeza old project5 (7 revisions)
- Transforming MemPool into a CGRA (M) (7 revisions)
- Development of an implantable Force sensor for orthopedic applications (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities (7 revisions)
- Extending the HERO SDK to support asynchronous offloading (M/1-3S) (7 revisions)
- Ultra-low power processor design (7 revisions)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (7 revisions)
- Satellite Internet of Things (7 revisions)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (7 revisions)
- SW/HW Predictability and Security (7 revisions)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (7 revisions)
- EEG artifact detection for epilepsy monitoring (7 revisions)
- Charging System for Implantable Electronics (7 revisions)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver (7 revisions)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (7 revisions)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (7 revisions)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (7 revisions)
