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- ...or to easily create such architectures. This project requires knowledge of digital logic and VLSI implementation. : 50% VLSI Design5 KB (653 words) - 11:08, 12 November 2020
- ...i, T. Goldstein, and C. Studer, "Finite-Alphabet MMSE Equalization for All-Digital Massive MU-MIMO mmWave Communication," IEEE Journal on Selected Areas in Co * '''[[Design Review]]'''6 KB (829 words) - 11:37, 12 November 2020
- * '''[[Design Review]]''' [[Category:Digital]]6 KB (748 words) - 13:57, 12 November 2020
- ...sing HDL. The developed HDL code will be synthesized and implemented as an ASIC after placement and routing. The breakdown of the tasks will be as follows: * Placement and routing of the synthesized design3 KB (389 words) - 01:43, 10 February 2021
- * 20% FPGA RTL design * RTL Design in SystemVerilog and Xilinx FPGA flow as taught in VLSI I11 KB (1,602 words) - 15:19, 9 July 2021
- [[Category:Digital]] [[Category:FPGA]]8 KB (1,220 words) - 15:18, 9 July 2021
- ...a 32-bit in-order RISC-V core implementing the RV32IC instruction set. Its design is of high-quality, open source and it comes with an industry-grade verific ...eed you to bring into the project is basic knowledge in integrated circuit design (VLIS I/II lectures), team working skills, self-motivation, drive and a pos6 KB (835 words) - 12:52, 27 April 2021
- * '''[[Design Review]]''' [[Category:Digital]]6 KB (687 words) - 13:32, 10 May 2023
- * Knowledge of digital arithmetic (e.g., two's complement, overflow, wraparound) [[Category:Digital]]5 KB (659 words) - 14:08, 15 February 2024
- ...s logic has blatant advantages over synchronous designs, asynchronous VLSI design was, up until now, not supported by EDA tools and, hence, enjoyed only limi ...ls available at [2]. Third, the student(s) will compare their asynchronous design to state-of-the-art synchronous LDPC decoders in the same process technolog6 KB (725 words) - 17:36, 20 October 2021
- ...conductor devices. As such, these architectures are often (i) difficult to design, test, or migrate to other technology nodes, due to their analog component, ...e, that it can achieve better area- and energy-efficiency than traditional digital architectures that perform the same operation. These results demonstrate th7 KB (933 words) - 19:29, 21 November 2021
- ...more, PPAC can achieve better area- and energy-efficiency than traditional digital architectures that perform the same operation. This project requires knowledge of digital logic and programming skills in C.7 KB (804 words) - 19:45, 21 November 2021
- * '''[[Design Review]]''' [[Category:Digital]]4 KB (520 words) - 14:52, 24 November 2021
- * '''[[Design Review]]''' [[Category:Digital]]5 KB (564 words) - 16:12, 9 February 2022
- * '''[[Design Review]]''' [[Category:Digital]]5 KB (586 words) - 16:15, 9 February 2022
- [[Category:Digital]] [[Category:Digital Medical Ultrasound Imaging]]7 KB (831 words) - 19:36, 12 January 2023
- In the first part of this project, you will re-design and refactor the existing C-BRED codebase to support additional graph dista [[Category:Digital]]6 KB (839 words) - 14:08, 15 February 2024
- * '''[[Design Review]]''' [[Category:Digital]]4 KB (503 words) - 13:54, 30 May 2022
- guessing accuracy, implement an architecture, and test it on an FPGA. : Familiarity with the basics of digital communication is recommended but not strictly required4 KB (470 words) - 18:16, 27 May 2022
- : Familiarity with the basics of digital communication is recommended but not strictly required * '''[[Design Review]]'''4 KB (492 words) - 10:55, 16 June 2022
- have to rely on low-resolution analog-to-digital converters (ADCs). However, the use of such low-resolution ADCs creates new ...G. Durisi, T. Goldstein, and C. Studer, "Hybrid Jammer Mitigation for All-Digital mmWave Massive MU-MIMO", 2021 Asilomar Conference on Signals, Systems, and5 KB (662 words) - 13:33, 10 May 2023
- * '''[[Design Review]]''' [[Category:Digital]]5 KB (586 words) - 15:34, 11 July 2022
- [[Category:Digital]] [[Category:ASIC]]8 KB (1,304 words) - 14:44, 23 October 2023
- [[Category:Digital]] [[Category:FPGA]]3 KB (416 words) - 10:49, 25 January 2024
- Digital sound synthesis is widely used in modern music production, with many popula The goals of this project are to design, optimize, and implement aliasing-free oscillator synchronization of arbitr5 KB (577 words) - 09:48, 5 October 2022
- [[Category:Digital]] ...-physical address translation. As it seems, it’s a very complex block to design and handle.5 KB (769 words) - 11:38, 3 November 2023
- [[Category:Digital]] ...itly defined in software, for which several DMA engines are provided. This design decision improves overall energy efficiency.7 KB (944 words) - 10:47, 25 January 2024
- <!-- Radiation Testing of a PULP ASIC (1S) --> [[Category:Digital]]3 KB (454 words) - 14:59, 25 October 2023
- ...ls, small rooms, caves, etc.) or improving realism. However, most existing digital signal processing (DSP)-based reverberation techniques require large amount The goal of this project is to design and implement a novel artificial reverberation algorithm that requires a mi5 KB (578 words) - 12:39, 14 June 2023
- <!-- FPGA mapping of RPC DRAM (1-2S/B) --> [[Category:Digital]]3 KB (484 words) - 20:29, 21 February 2024
- ...ed FPGA/GPU based system with a compact, and incubator-compatible hardware design. [[Image:Hangxing FPGA.png|800px| System Overview]]6 KB (720 words) - 16:27, 27 September 2023
- : Embedded systems and PCB design * '''[[Design Review]]'''6 KB (688 words) - 12:15, 23 July 2023
- ...g the speed and design effort bottlenecks of cycle-accurate simulators and FPGA prototypes, respectively, while preserving functional and timing accuracy. ...show that GVSoC enables practical functional and performance analysis and design exploration at the full-platform level (processors, memory, peripherals and14 KB (2,018 words) - 22:54, 23 November 2023
- : Embedded systems and PCB design : 40% Hardware and PCB Design6 KB (735 words) - 12:15, 23 July 2023
- : 30% Mechanical Design ...of coupling media in terms of: acoustic properties (e.g., attenuation), 3d design and integration, farbication complexity, cost.5 KB (631 words) - 12:43, 23 July 2023
- * Showing participation in non-curricular analog/digital projects is a plus. * Circuit design tools (e.g., Altium Designer).7 KB (903 words) - 10:04, 24 July 2023
- : 30% Mechanical Design ...of coupling media in terms of: acoustic properties (e.g., attenuation), 3d design and integration, farbication complexity, cost.5 KB (631 words) - 10:07, 24 July 2023
- ...hoice for DNN implementation, more exotic accelerators including dedicated ASIC designs and in-memory based designs have also been proposed. ...or-Matrix Multiplications (VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at signific3 KB (356 words) - 14:53, 11 October 2023
- [[Category:Digital]] [[Category:ASIC]]2 KB (314 words) - 18:47, 24 November 2023