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  • ASIC Design of a Gaussian Message Passing Processor
    ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
    1 KB (210 words) - 08:34, 20 January 2021
  • Analog
    ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor ...he field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless t
    3 KB (369 words) - 18:11, 1 March 2023
  • ASIC Design of a Sigma Point Processor
    ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
    2 KB (265 words) - 08:34, 20 January 2021
  • Android reliability governor
    Dynamic Reliability Management (DRM) techniques aims at trading-off processor performance with lifetime at run-time by modulating the working temperature
    4 KB (573 words) - 17:24, 9 February 2015
  • Design of an LTE Module for the Internet of Things
    [[Category:Processor]]
    3 KB (335 words) - 14:20, 4 November 2019
  • Design and Implementation of a Convolutional Neural Network Accelerator ASIC
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    9 KB (1,289 words) - 19:45, 24 March 2015
  • Low-power Clock Generation Solutions for 65nm Technology
    operating voltage, the clock rate of such a processor will be between
    3 KB (466 words) - 19:37, 3 March 2016
  • Evaluating the RiscV Architecture
    [[Category:Processor]]
    3 KB (374 words) - 16:24, 30 October 2020
  • Hardware/software co-programming on the Parallella platform
    ...power platform similar to the Raspberry Pi. It features a dual-core ARM A9 processor running Linux, a powerful FPGA and a 16-core accelerator chip called "Epiph
    3 KB (501 words) - 14:26, 2 September 2015
  • Gomeza old project1
    # Characterization of the time/memory overhead incurred by the inter-processor communication.
    3 KB (431 words) - 18:04, 28 January 2017
  • Acceleration and Transprecision
    ...e the backbone of big data and scientific computing. While general purpose processor architectures such as Intel's x86 provide good performance across a wide va
    2 KB (275 words) - 17:05, 24 November 2023
  • Linear Solvers for Image and Video Processing Applications
    #REDIRECT [[DMA Streaming Co-processor]]
    40 bytes (4 words) - 18:10, 14 April 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. ...n allows the programmer to share virtual address pointers between the host processor and the accelerator in a completely transparent manner, it still requires t
    5 KB (716 words) - 13:43, 29 November 2019
  • Vector Processor for In-Memory Computing
    ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design
    3 KB (443 words) - 13:10, 2 November 2015
  • FFT-based Convolutional Network Accelerator
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    8 KB (1,145 words) - 11:30, 5 February 2016
  • High-speed Scene Labeling on FPGA
    ...the types of layer in the ConvNet, interaction between a flow controlling processor (e.g. an ARM core on a Xilinx Zynq) and the programmable logic is foreseen. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    8 KB (1,197 words) - 18:18, 29 August 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
    4 KB (585 words) - 17:57, 7 November 2017
  • PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
    4 KB (554 words) - 17:57, 7 November 2017
  • Digital Audio Processor for Cellular Applications
    ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
    1 KB (229 words) - 18:01, 29 March 2017
  • Switched Capacitor Based Bandgap-Reference
    [[Category:Processor]]
    4 KB (471 words) - 11:13, 3 May 2018
  • Baseband Processor Development for 4G IoT
    The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform
    2 KB (347 words) - 17:58, 14 April 2016
  • An FPGA-Based Testbed for 4G/LTE Mobile Communication
    #REDIRECT [[Baseband Processor Development for 4G IoT]]
    55 bytes (7 words) - 14:46, 28 May 2015
  • Improving our Smart Camera System
    ...X1 board to get best performance transferring data from the sensor to the processor. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    8 KB (1,176 words) - 16:26, 30 October 2020
  • System Analysis and VLSI Design of NB-IoT Baseband Processing
    [[File:lteTestbed.jpg|thumb|Figure 2: LTE testbed with digital baseband and processor on an FPGA and RF-IC on the [[evaLTE]] FMC module.]]
    2 KB (245 words) - 10:39, 6 November 2017
  • Implementing Hibernation on the ARM Cortex M0
    ...ailable before the power outage, i.e., the supply voltage is dropping, the processor state can be saved only when a power outage is imminent and thus superfluou Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibe
    3 KB (390 words) - 11:59, 20 June 2016
  • Design of State Retentive Flip-Flops
    ...ation to be retained between two calls, it is not acceptable for an entire processor core idling, for example while waiting for a DMA transfer to be completed.
    2 KB (364 words) - 09:34, 25 July 2017
  • Standard Cell Compatible Memory Array Design
    ...ocks of any processing system, in fact most of the performance of a modern processor is determined by its ability to efficiently store and retrieve data. For IC
    5 KB (769 words) - 15:54, 23 May 2018
  • Intelligent Power Management Unit (iPMU)
    ...PMU should schedule the system tasks in an optimal way and wakeup the main processor if required. Naturally, the iPMU should consume as little power as possible
    2 KB (292 words) - 11:40, 2 June 2021
  • Change-based Evaluation of Convolutional Neural Networks
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    5 KB (747 words) - 18:04, 29 August 2016
  • Rethinking our Convolutional Network Accelerator Architecture
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    9 KB (1,263 words) - 18:52, 12 December 2016
  • Design of a VLIW processor architecture based on RISC-V
    ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
    3 KB (377 words) - 10:25, 5 November 2019
  • Minimal Cost RISC-V core
    ...n are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is enough. A very simple 2-3stag ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
    3 KB (384 words) - 17:24, 21 August 2019
  • Turbo Equalization for Cellular IoT
    [[Category:Processor]]
    3 KB (450 words) - 11:43, 13 November 2018
  • PULPonFPGA: Hardware L2 Cache
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
    5 KB (711 words) - 10:27, 5 November 2019
  • NextGenChannelDec
    [[Category:Processor]]
    3 KB (402 words) - 15:31, 13 April 2016
  • Next Generation Channel Decoder
    [[Category:Processor]]
    3 KB (418 words) - 14:01, 13 November 2020
  • Implementation of a NB-IoT Positioning System
    ...ftware co-design in which part of the algorithm will be mapped onto a PULP processor while computational complex tasks are realized in dedicated hardware accele [[Category:Processor]]
    4 KB (555 words) - 16:36, 23 May 2018
  • Design of a Fused Multiply Add Floating Point Unit
    ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.
    2 KB (346 words) - 10:26, 5 November 2019
  • PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
    5 KB (712 words) - 17:57, 7 November 2017
  • PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
    6 KB (866 words) - 13:43, 29 November 2019
  • Towards The Integration of E-skin into Prosthetic Devices
    ...sensors and one or two algorithms will be implemented directly in the PULP processor. One of main challenging goal of the project is bring these algorithm in an * programming the PULP processor for the specific application, otimize the code and carry out in-field testi
    4 KB (631 words) - 11:39, 21 July 2017
  • Bringing XNOR-nets (ConvNets) to Silicon
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    10 KB (1,357 words) - 16:25, 30 October 2020
  • Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
    *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]
    3 KB (351 words) - 16:19, 27 February 2018
  • Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
    ...m the ADC HW-FIFO to SW-FIFO at kernel-space and the real-time embedded co-processor ([http://beagleboard.org/pru PRU]) for post-processing of the data-stream. *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet]
    3 KB (394 words) - 16:19, 27 February 2018
  • Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
    *[http://www.ti.com/lit/ds/symlink/am3358.pdf AM335x Sitara Processor Datasheet] *[http://www.ti.com/lit/ug/spruh73n/spruh73n.pdf AM335x Sitara Processor TRM]
    3 KB (440 words) - 16:15, 1 September 2017
  • PVT Dynamic Adaptation in PULPv3
    ...mic power controller algorithm is then needed to always configure the PULP processor in the most energy efficient point.
    3 KB (348 words) - 15:31, 13 September 2016
  • On-chip clock synthesizer design and porting
    ...ps (SoCs) often consist of various independent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking
    3 KB (389 words) - 11:20, 14 September 2016
  • Efficient NB-IoT Uplink Design
    while the DBB processing can be done in a CPU, a Digital Signal Processor (DSP), an Appli- Open-RISC processor. The processor can be used to control the baseband blocks as well as to
    6 KB (900 words) - 16:58, 7 May 2018
  • Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
    ...ystems Laboratory (IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-
    9 KB (1,427 words) - 18:36, 5 September 2019
  • VLSI Implementation Polar Decoder using High Level Synthesis
    [[Category:Processor]]
    3 KB (392 words) - 14:17, 5 April 2022

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