Short pages
From iis-projects
Showing below up to 100 results in range #1 to #100.
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- (hist) Deconvolution Accelerator for On-Chip Semi-Supervised Learning [0 bytes]
- (hist) Neural Processing [0 bytes]
- (hist) Near-Memory Training of Neural Networks [0 bytes]
- (hist) Biomedical System on Chips [0 bytes]
- (hist) Mattia [0 bytes]
- (hist) Enabling Standalone Operation [0 bytes]
- (hist) Optimal System Duty Cycling [0 bytes]
- (hist) Implementation of a Heterogeneous System for Image Processing on an FPGA [0 bytes]
- (hist) Palm size chip NMR [0 bytes]
- (hist) A Snitch-based Compute Accelerator for HERO [0 bytes]
- (hist) (M): A Flexible Peripheral System for High-Performance Systems on Chip [0 bytes]
- (hist) IBM Research–Zurich [0 bytes]
- (hist) DaCe on Snitch [0 bytes]
- (hist) SSR combined with FREP in LLVM/Clang [0 bytes]
- (hist) IBM A2O Core [0 bytes]
- (hist) IP-Based SoC Generation and Configuration (1-3S) [0 bytes]
- (hist) MemPool on HERO [0 bytes]
- (hist) ISA extensions in the Snitch Processor for Signal Processing (1M) [0 bytes]
- (hist) Integrating Hardware Accelerators into Snitch [0 bytes]
- (hist) Prasadar [0 bytes]
- (hist) On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks [0 bytes]
- (hist) Test project [0 bytes]
- (hist) Benchmarking a heterogeneous 217-core MPSoC on HPC applications [0 bytes]
- (hist) Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) [0 bytes]
- (hist) A Post-Simulation Trace-Based RISC-V GDB Debugging Server [0 bytes]
- (hist) Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) [0 bytes]
- (hist) Versatile HW SW Digital PHY for inter chip communication [0 bytes]
- (hist) Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) [0 bytes]
- (hist) Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) [0 bytes]
- (hist) Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) [0 bytes]
- (hist) Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) [0 bytes]
- (hist) Test page [16 bytes]
- (hist) A Trustworthy Three-Factor Authentication System [40 bytes]
- (hist) Influence of the Initial FilamentGeometry on the Forming Step in CBRAM [75 bytes]
- (hist) Theory, Algorithms, and Hardware for Beyond 5G [120 bytes]
- (hist) Positioning with Wireless Signals [121 bytes]
- (hist) All-Digital In-Memory Processing [121 bytes]
- (hist) Real-Time Optimization [121 bytes]
- (hist) Audio Signal Processing [123 bytes]
- (hist) Simultaneous Sensing and Communication [123 bytes]
- (hist) Mixed-Signal Circuit Design [123 bytes]
- (hist) Analog IC Design [130 bytes]
- (hist) Mixed Signal IC Design [136 bytes]
- (hist) AnalogInt [343 bytes]
- (hist) Atretter [362 bytes]
- (hist) Tbenz [362 bytes]
- (hist) Audio [403 bytes]
- (hist) Taimir Aguacil [416 bytes]
- (hist) Christoph Keller [423 bytes]
- (hist) Project Meetings [425 bytes]
- (hist) Project Plan [453 bytes]
- (hist) Moritz Schneider [459 bytes]
- (hist) Software [473 bytes]
- (hist) Stefan Lippuner [532 bytes]
- (hist) Benjamin Sporrer [567 bytes]
- (hist) Philipp Schönle [569 bytes]
- (hist) Design Review [577 bytes]
- (hist) Nils Wistoff [578 bytes]
- (hist) Mauro Salomon [637 bytes]
- (hist) Cryptography [645 bytes]
- (hist) Libria [646 bytes]
- (hist) Karim Badawi [653 bytes]
- (hist) Matthias Korb [698 bytes]
- (hist) Energy Efficient Circuits and IoT Systems Group [736 bytes]
- (hist) EECIS [740 bytes]
- (hist) Harald Kröll [764 bytes]
- (hist) Pascal Hager [775 bytes]
- (hist) Research [789 bytes]
- (hist) Ultrasound [797 bytes]
- (hist) Federico Villani [834 bytes]
- (hist) Coding Guidelines [841 bytes]
- (hist) Herschmi [859 bytes]
- (hist) Matheus Cavalcante [890 bytes]
- (hist) Telecommunications [892 bytes]
- (hist) Benjamin Weber [894 bytes]
- (hist) Norbert Felber [897 bytes]
- (hist) Christoph Leitner [928 bytes]
- (hist) Robert Balas [931 bytes]
- (hist) GRAND Hardware Implementation [990 bytes]
- (hist) FPGA [1,020 bytes]
- (hist) Matteo Perotti [1,028 bytes]
- (hist) Andreas Kurth [1,029 bytes]
- (hist) Fabian Schuiki [1,031 bytes]
- (hist) Stefan Mach [1,044 bytes]
- (hist) Eye tracking [1,058 bytes]
- (hist) Integrated Devices, Electronics, And Systems [1,058 bytes]
- (hist) Frank K. Gürkaynak [1,072 bytes]
- (hist) Low-Power Time Synchronization for IoT Applications [1,085 bytes]
- (hist) Physical Layer Implementation of HSPA+ 4G Mobile Transceiver [1,088 bytes]
- (hist) Guillaume Mocquard [1,117 bytes]
- (hist) Final Presentation [1,130 bytes]
- (hist) Channel Estimation for 3GPP TD-SCDMA [1,144 bytes]
- (hist) Synchronization and Power Control Concepts for 3GPP TD-SCDMA [1,145 bytes]
- (hist) Michael Muehlberghuber [1,160 bytes]
- (hist) An FPGA-Based Testbed for 3G Mobile Communications Receivers [1,168 bytes]
- (hist) FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications [1,194 bytes]
- (hist) Michael Rogenmoser [1,211 bytes]
- (hist) Interference Cancellation for EC-GSM-IoT [1,281 bytes]
- (hist) Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) [1,284 bytes]
- (hist) ASIC [1,286 bytes]