Orphaned pages
From iis-projects
The following pages are not linked from or transcluded into other pages in iis-projects.
Showing below up to 50 results in range #231 to #280.
View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)
- Edge Computing for Long-Term Wearable Biomedical Systems
- Efficient Banded Matrix Multiplication for Quantum Transport Simulations
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Implementation of an Active-Set QP Solver for FPGAs
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient NB-IoT Uplink Design
- Efficient Search Design for Hyperdimensional Computing
- Efficient Synchronization of Manycore Systems (M/1S)
- Efficient TNN Inference on PULP Systems
- Efficient TNN compression
- Efficient collective communications in FlooNoC (1M)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap
- Elliptic Curve Accelerator for zkSNARKs
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Enabling Efficient Systolic Execution on MemPool (M)
- Enabling Standalone Operation
- Enabling Standalone Operation for a Mobile Health Platform
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Efficient SoCs
- Engineering For Kids
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Event-based navigation on autonomous nano-drones
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
