Category:In progress
From iis-projects
These projects are currently running.
- ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
- ASR-Waveformer
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Fault-Tolerant Floating-Point Units (M)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Implementation of a Cache Reliability Mechanism (1S/M)
- Efficient collective communications in FlooNoC (1M)
- On-Board Software for PULP on a Satellite
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Zephyr RTOS on PULP
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Physical Implementation of ITA (2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Virtual Memory Ara
- New RVV 1.0 Vector Instructions for Ara
- Big Data Analytics Benchmarks for Ara
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Runtime partitioning of L1 memory in Mempool (M)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Radiation Testing of a PULP ASIC
- On - Device Continual Learning for Seizure Detection on GAP9
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
- ASIC implementation of an interpolation-based wideband massive MIMO detector
- Jammer Mitigation Meets Machine Learning
- Jammer-Resilient Synchronization for Wireless Communications
- Ternary Neural Networks for Face Recognition
- Machine Learning Assisted Direct Synthesis of Passive Networks
- Super Resolution Radar/Imaging at mm-Wave frequencies
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Efficient TNN compression
- Event-Driven Vision on an embedded platform
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- Pulse Oximetry Fachpraktikum
- IcySoC
Pages in category "In progress"
The following 39 pages are in this category, out of 39 total.
A
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- ASIC Development of 5G-NR LDPC Decoder
- ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
- ASIC implementation of an interpolation-based wideband massive MIMO detector
- ASR-Waveformer