Category:High Performance SoCs
From iis-projects
Revision as of 13:00, 2 November 2020 by Tbenz (talk | contribs) (Redirected page to High Performance SoCs)
Redirect page
The printable version is no longer supported and may have rendering errors. Please update your browser bookmarks and please use the default browser print function instead.
Redirect to:
Pages in category "High Performance SoCs"
The following 98 pages are in this category, out of 98 total.
A
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Unified Compute Kernel Library for Snitch (1-2S)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- All the flavours of FFT on MemPool (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- AXI-based Network on Chip (NoC) system
B
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Big Data Analytics Benchmarks for Ara
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
C
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S)
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Cycle-Accurate Event-Based Simulation of Snitch Core
D
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
E
- Efficient collective communications in FlooNoC (1M)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- Efficient Synchronization of Manycore Systems (M/1S)
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the HERO SDK to support asynchronous offloading (M/1-3S)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
F
I
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementing DSP Instructions in Banshee (1S)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (M)
M
O
P
R
S
T
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Transforming MemPool into a CGRA (M)
