Pages with the fewest revisions
From iis-projects
Showing below up to 250 results in range #251 to #500.
View (previous 250 | next 250) (20 | 50 | 100 | 250 | 500)
- Wireless Biomedical Signal Acquisition Device (4 revisions)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (4 revisions)
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node (4 revisions)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (4 revisions)
- Theory, Algorithms, and Hardware for Beyond 5G (4 revisions)
- Smart e-glasses for concealed recording of EEG signals (4 revisions)
- Intelligent Power Management Unit (iPMU) (4 revisions)
- Ibex: Bit-Manipulation Extension (4 revisions)
- Power Optimization in Multipliers (4 revisions)
- Improving our Smart Camera System (4 revisions)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (4 revisions)
- Enhancing our DMA Engine with Fault Tolerance (4 revisions)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (4 revisions)
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications (4 revisions)
- ASIC Design of a Sigma Point Processor (4 revisions)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (4 revisions)
- In-ear EEG signal acquisition (4 revisions)
- CPS Software-Configurable State-Machine (4 revisions)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets (4 revisions)
- Accelerating Applications Relying on Matrix-Vector-Product-Like Operations (4 revisions)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (4 revisions)
- Low-power chip-to-chip communication network (4 revisions)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (4 revisions)
- High performance continous-time Delta-Sigma ADC for biomedical applications (4 revisions)
- Palm size chip NMR (4 revisions)
- Final Report (4 revisions)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (4 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (4 revisions - redirect page)
- Forward error-correction ASIC using GRAND (4 revisions)
- Telecommunications (4 revisions)
- Ultra-low power sampling front-end for acquisition of physiological signals (4 revisions)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) (4 revisions)
- NAND Flash Open Research Platform (4 revisions)
- Ultrasound High Speed Microbubble Tracking (4 revisions)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (4 revisions)
- Adding Linux Support to our DMA engine (1-2S/B) (4 revisions - redirect page)
- Stefan Lippuner (4 revisions)
- Virtual Memory Ara (4 revisions)
- SSR combined with FREP in LLVM/Clang (M/1-3S) (4 revisions - redirect page)
- Sub-Noise Floor Channel Tracking (4 revisions)
- Pascal Hager (4 revisions)
- Implementation of an AES Hardware Processing Engine (B/S) (4 revisions)
- Eye movements (4 revisions)
- Stefan Mach (4 revisions)
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM (4 revisions)
- Finite element modeling of electrochemical random access memory (4 revisions)
- Advanced Data Movers for Modern Neural Networks (4 revisions)
- EEG artifact detection with machine learning (4 revisions)
- Efficient TNN compression (4 revisions)
- Jammer-Resilient Synchronization for Wireless Communications (4 revisions)
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks (4 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core (4 revisions)
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications (4 revisions)
- Noise Figure Measurement for Cryogenic System (5 revisions)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography (5 revisions)
- Internet of Things SoC Characterization (5 revisions)
- Toward Superposition of Brain-Computer Interface Models (5 revisions)
- Ultra Low Power Conversion Circuit For Batteryless Applications (5 revisions)
- Embedded Systems and autonomous UAVs (5 revisions)
- Data Augmentation Techniques in Biosignal Classification (5 revisions)
- IP-Based SoC Generation and Configuration (1-3S/B) (5 revisions)
- LightProbe - Thermal-Power aware on-head Beamforming (5 revisions)
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration (5 revisions)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (5 revisions)
- Ultra Low Power Wake Up Radio for Wireless Sensor Network (5 revisions)
- Predictable Execution on GPU Caches (5 revisions)
- Hardware Accelerator for Model Predictive Controller (5 revisions)
- Ultrasound signal processing acceleration with CUDA (5 revisions)
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor (5 revisions)
- Towards Autonomous Navigation for Nano-Blimps (5 revisions)
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA) (5 revisions)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (5 revisions)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (5 revisions)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (5 revisions)
- Engineering For Kids (5 revisions)
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device (5 revisions)
- TCNs vs. LSTMs for Embedded Platforms (5 revisions)
- ASIC Design Projects (5 revisions)
- A Wearable System To Control Phone And Electronic Device Without Hands (5 revisions)
- Ultrafast Medical Ultrasound imaging on a GPU (5 revisions)
- Low-power Clock Generation Solutions for 65nm Technology (5 revisions)
- Federico Villani (5 revisions)
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path (5 revisions)
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) (5 revisions)
- Design and Implementation of ultra low power vision system (5 revisions)
- Universal Stream Semantic Registers for Snitch (1S) (5 revisions - redirect page)
- Phase-change memory devices for emerging computing paradigms (5 revisions)
- Fast Simulation of Manycore Systems (1S) (5 revisions)
- Snitch meets iCE40 (1-2S/B) (5 revisions - redirect page)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich) (5 revisions)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea (5 revisions)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (5 revisions)
- Compression of Ultrasound data on FPGA (5 revisions)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap (5 revisions)
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC (5 revisions)
- Final Presentation (5 revisions)
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers (5 revisions)
- Artificial Reverberation for Embedded Systems (5 revisions)
- Implementation of a NB-IoT Positioning System (5 revisions)
- LLVM and DaCe for Snitch (1-2S) (5 revisions)
- Channel Shortening Prefilter (5 revisions - redirect page)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (5 revisions)
- Adding Linux Support to our DMA Engine (1-2S/B) (5 revisions)
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces (5 revisions)
- Resource Partitioning of Caches (5 revisions)
- State-Saving @ NXP (5 revisions)
- A Wireless Sensor Network for a Smart Building Monitor and Control (5 revisions)
- Indoor Smart Tracking of Hospital instrumentation (5 revisions)
- Beat DigRF (5 revisions)
- Open Power-On Chip Controller Study and Integration (5 revisions)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) (5 revisions)
- Low Latency Brain-Machine Interfaces (5 revisions)
- IBM A2O Core (5 revisions)
- Designing a Power Management Unit for PULP SoCs (5 revisions)
- Simulation of 2D artificial cilia metasurface in COMSOL (5 revisions)
- Ultra-low power transceiver for implantable devices (5 revisions)
- Image Sensor Interface and Pre-processing (5 revisions)
- Inductive Charging Circuit for Implantable Devices (5 revisions)
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control (5 revisions)
- Hardware/software codesign neural decoding algorithm for “neural dust” (5 revisions)
- An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications (5 revisions)
- Embedded Artificial Intelligence:Systems And Applications (5 revisions)
- Software-Defined Paging in the Snitch Cluster (2-3S) (5 revisions)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (5 revisions)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (5 revisions)
- Machine Learning for extracting Muscle features from Ultrasound raw data (5 revisions)
- FPGA Testbed Implementation for Bluetooth Indoor Positioning (5 revisions)
- Ternary Neural Networks for Face Recognition (5 revisions)
- Design of a Fused Multiply Add Floating Point Unit (5 revisions)
- Development of an efficient algorithm for quantum transport codes (5 revisions)
- Precise Ultra-low-power Timer (5 revisions)
- Low-Complexity MIMO Detection (5 revisions)
- Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) (5 revisions)
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams (5 revisions)
- Eye tracking (5 revisions)
- 5G Cellular RF Front-end Design in 22nm CMOS Technology (5 revisions)
- Andreas Kurth (5 revisions)
- LightProbe - Frontend Firmware and Control Side Channel (5 revisions)
- Predict eye movement through brain activity (5 revisions)
- Subject specific embeddings for transfer learning in brain-computer interfaces (5 revisions)
- Learning Image Compression with Convolutional Networks (5 revisions)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (5 revisions)
- Android Software Design (6 revisions)
- FPGA mapping of RPC DRAM (6 revisions)
- Moritz Schneider (6 revisions)
- Design of a Low Power Smart Sensing Multi-modal Vision Platform (6 revisions)
- Learning Image Decompression with Convolutional Networks (6 revisions)
- System Emulation for AR and VR devices (6 revisions)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (6 revisions)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (6 revisions)
- Graph neural networks for epileptic seizure detection (6 revisions)
- Enabling Efficient Systolic Execution on MemPool (M) (6 revisions)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (6 revisions)
- LightProbe - Ultracompact Power Supply PCB (6 revisions)
- Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening (6 revisions)
- Channel Estimation for 3GPP TD-SCDMA (6 revisions)
- New RVV 1.0 Vector Instructions for Ara (6 revisions)
- Implementing Configurable Dual-Core Redundancy (6 revisions)
- Autonomous Smart Watches: Hardware and Software Desing (6 revisions)
- Creating a HDMI Video Interface for PULP (6 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (6 revisions)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (6 revisions)
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets (6 revisions)
- MemPool on HERO (1S) (6 revisions)
- Implementing DSP Instructions in Banshee (1S) (6 revisions)
- Ultra-Efficient Visual Classification on Movidius Myriad2 (6 revisions)
- CMOS power amplifier for field measurements in MRI systems (6 revisions)
- Low-power Temperature-insensitive Timer (6 revisions)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (6 revisions)
- Switched Capacitor Based Bandgap-Reference (6 revisions)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich) (6 revisions)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (6 revisions)
- Bluetooth Low Energy receiver in 65nm CMOS (6 revisions)
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing (6 revisions)
- Novel Metastability Mitigation Technique (6 revisions)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA (6 revisions)
- A Recurrent Neural Network Speech Recognition Chip (6 revisions)
- Improved Collision Avoidance for Nano-drones (6 revisions)
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things (6 revisions)
- Floating-Point Divide & Square Root Unit for Transprecision (6 revisions)
- Novel Methods for Jammer Mitigation (6 revisions)
- Beat Cadence (6 revisions)
- Exploring Algorithms for Early Seizure Detection (6 revisions)
- Compression of iEEG Data (6 revisions)
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA (6 revisions)
- VLSI Design of an Asynchronous LDPC Decoder (6 revisions)
- FPGA Optimizations of Dense Binary Hyperdimensional Computing (6 revisions)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (6 revisions)
- Exploring NAS spaces with C-BRED (6 revisions)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (6 revisions)
- Next Generation Channel Decoder (6 revisions)
- Writing a Hero runtime for EPAC (1-3S/B) (6 revisions)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (6 revisions)
- Efficient Synchronization of Manycore Systems (M/1S) (6 revisions)
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors (6 revisions)
- Towards Self Sustainable UAVs (6 revisions)
- Self Aware Epilepsy Monitoring (6 revisions)
- VLSI Implementation of a 5G Ciphering Accelerator (6 revisions)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) (6 revisions)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (6 revisions)
- IBM Research–Zurich (6 revisions)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (6 revisions)
- Change-based Evaluation of Convolutional Neural Networks (6 revisions)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (6 revisions)
- Ultrasound image data recycler (6 revisions)
- EEG earbud (7 revisions)
- Gomeza old project5 (7 revisions)
- Development of statistics and contention monitoring unit for PULP (7 revisions)
- Predictable Execution (7 revisions)
- Satellite Internet of Things (7 revisions)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (7 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (7 revisions)
- Charging System for Implantable Electronics (7 revisions)
- Outdoor Precision Object Tracking for Rockfall Experiments (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (7 revisions)
- Mauro Salomon (7 revisions)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (7 revisions)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
- Bateryless Heart Rate Monitoring (7 revisions)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (7 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Make Cellular Internet of Things Receivers Smart (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (7 revisions)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Battery indifferent wearable Ultrasound (7 revisions)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (7 revisions)
- Ultrasound-EMG combined hand gesture recognition (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (7 revisions)
- Ultra-low power processor design (7 revisions)
- Development of a Rockfall Sensor Node (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Efficient Search Design for Hyperdimensional Computing (7 revisions)
- Ultrasound Low power WiFi with IMX7 (7 revisions)
