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• Template
  [[Category:Computer Architecture]] [[Category:Acceleration and Transprecision]]
  4 KB (397 words) - 15:44, 14 February 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  ...electric polarization in the material by reorienting the crystal structure and aligning the electric dipoles in the direction of the electric field. ...ure in such a way that later studies will allow '''ML-based control of the system'''.
  6 KB (741 words) - 18:14, 21 July 2023
• Digitally-Controlled Analog Subtractive Sound Synthesis
  ..., etc. In recent years, building such music synthesizers became accessible and affordable as companies, e.g. Sound Semiconductor [1] or Coolaudio [2], man ...s) will first familiarize themselves with the ICs from Sound Semiconductor and then, manufacture a printed circuit board (PCB) that implements the subtrac
  5 KB (597 words) - 12:56, 4 December 2021
• Accelerator for Boosted Binary Features
  [[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]] Image feature extraction is an important analysis tool in many computer vision applications. In the context of this project, it is specifically use
  3 KB (373 words) - 11:51, 19 August 2017
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  ...ther fields. An interesting approach is that followed by the IBM TrueNorth architecture [Merolla14], an homogeneous fabric of 1 million digital spiking neurons tha ...ltra-low-power computing cluster composed of fully programmable RISC cores and traditional coprocessors/accelerators.
  5 KB (784 words) - 14:50, 30 November 2016
• Digital
  rect 0 910 1300 1820 [[Biomedical Circuits, Systems, and Applications]] rect 2600 0 3900 910 [[HW/SW Safety and Security]]
  7 KB (816 words) - 11:57, 8 May 2024
• High-speed Scene Labeling on FPGA
  ...h-speed implementations of synthetic vision systems capable of recognizing and classifying objects in a scene. Many popular algorithms in this area requir ...s much more applicable in industry and less constrained in terms of memory and interfaces. If desired by the student, also the use of high-level synthesis
  8 KB (1,197 words) - 18:18, 29 August 2016
• Improving our Smart Camera System
  ...s to process the acquired images faster based on the mostly static scenery and a second, multispectral camera module. ...mmunication capabilities to transmit suspicious cases to a remote computer and/or to add additional sensors (GPS, microphone). We would also like to port
  8 KB (1,176 words) - 16:26, 30 October 2020
• Design of a VLIW processor architecture based on RISC-V
  ...tructions), 48b, and 64b instructions. Our core is already supporting 16b, and 32b instructions, but as we have single-issue, in-order pipeline, the cores Moving to a very long instruction word (VLIW) architecture has several interesting advantages.
  3 KB (377 words) - 10:25, 5 November 2019
• Minimal Cost RISC-V core
  ...e currently supports the basic instruction set, as well as multiplications and divisions. To further increase the efficiency of the core we have also adde ...supports the basic instructions is enough. A very simple 2-3stage pipeline and minimal support for the number of registers can further decrease the power
  3 KB (384 words) - 17:24, 21 August 2019
• Fast Wakeup From Deep Sleep State
  [[File:Ap fulmine arch.png|400px|thumb|right|Architecture with reusable IPs highlighted]] ...pplication areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces.
  2 KB (236 words) - 08:35, 20 January 2021
• Design of a Fused Multiply Add Floating Point Unit
  ...''PULP''. Since it is a simple architecture, it consumes only little area and gives only little area savings when it is shared in a cluster. ...architecture for a fused multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.
  2 KB (346 words) - 10:26, 5 November 2019
• Open Power-On Chip Controller Study and Integration
  ...ed the Open-Power consortium, where a set of interested partners shares HW and SW IPs to create competitive computing node systems. ...on and firmware of the power 8 OCC allowing the implementation of advanced and custom-made power management features.
  3 KB (462 words) - 15:57, 9 September 2016
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...icularly on sensors that have a high need for extremely low power envelope and overall energy consumption, but at the same time can benefit from the avail ...ormation for us to recognize natural sounds, phonemes (and thus language), and music.
  9 KB (1,427 words) - 18:36, 5 September 2019
• Single-Bit-Synapse Spiking Neural System-on-Chip
  ...ther fields. An interesting approach is that followed by the IBM TrueNorth architecture [Merolla14], a homogeneous fabric of 1 million digital spiking neurons that ...his project we would like to develop a concrete proof of concept low power System-on-Chip where (small) practical applications such as Spiking Convolutional
  7 KB (1,000 words) - 12:22, 13 January 2017
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...high level semantically rich information out of raw data is deep learning, and in particular deep convolutional neural networks (CNNs). The task of infere ...design a PULP-based entire computation cluster around a set of deep, fast and low-power deep learning engines.
  6 KB (949 words) - 13:41, 10 November 2020
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  ...n than packed single-instruction multiple-data extensions (e.g. Intel AVX) and GPU-like single-instruction multiple-thread approaches to parallelism. ...-Riscy, one of the smallest RISC-V cores introduced at IIS [Schiavone2017] and use it as a baseline.
  6 KB (916 words) - 15:50, 7 December 2018
• Deep Learning for Brain-Computer Interface
  ...ever expanding applications suggesting its usage for a highly-accrue brain-computer interface. ...ct is to develop an algorithm based on deep learning for noninvasive brain-computer interfaces to classify EEG signals. The next step focuses on an efficient h
  3 KB (372 words) - 20:22, 1 April 2019
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
  ...in many fields, redefining the state of the art for computer vision, text and speech recognition, problem solving. Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art visual processing tasks.
  7 KB (1,001 words) - 10:43, 26 June 2017
• Trace Debugger for custom RISC-V Core
  ...f software development. It furthermore aids in bringing up silicon quickly and makes a software developer's life a lot easier. In smaller processors like ...ctual execution flow but break it into smaller pieces like halting the CPU and flushing certain data-structures.
  5 KB (729 words) - 11:27, 11 December 2018
• Creating a HDMI Video Interface for PULP
  ...ns. Unfortunately at the moment we are lacking any serious user-interfaces and we are constantly falling back to a standard UART (serial) interface. Your task would consist of interfacing such a transmitter and supplying it with data from an on-chip (or external) frame-buffer. At first
  4 KB (603 words) - 09:37, 10 July 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...partment of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real world, then this is your chance ...The Xilinx AC701 Development Board in combination with a recently designed and build interface board (see picture) will be used for the project. The work
  4 KB (460 words) - 21:42, 30 January 2018
• Aliasing-Free Wavetable Music Synthesizer
  ...esizers, such as the Waldorf Quantum, the UDO SUPER 6, the ASM hydrasynth, and the Nord Wave 2 (just to name a few). While most of these synthesizers rely ...while offering great flexibility. In the second step, a VLSI architecture and ASIC will be designed. The goal is to include easy reconfigurability of the
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  ...of "operators," which describe how various (typically 4-to-8) oscillators and envelope generators interact with each other. This project will develop the ...d, the student(s) will implement the architecture in a modern CMOS process and send the modular FM synthesis ASIC to fabrication.
  5 KB (549 words) - 12:35, 28 November 2022
• Hyperdimensional Computing
  ...arallel operations and is extremely robust against most failure mechanisms and noise. ...ng a prime candidate for utilization in application domains such as: brain-computer interfaces, biosignal processing (e.g., EEG/ECoG/EMG), robotics, voice/vide
  10 KB (1,341 words) - 10:46, 25 April 2018
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...uperconducting circuits by the implementation of optimal linear processing and thresholding of measured signals, followed by signal histogram generation a ...nal processing results. The interface between the FPGA and ADC board, DDR3 and PC is already implemented.
  5 KB (599 words) - 09:03, 21 December 2017
• Extend the RI5CY core with priviledge extensions
  ...rs that implements the RISC-V ISA. It has been designed for small embedded system platforms mostly used in IoT devices. Its ISA implements RISC-V's RV32IMFC Recently RI5CY as well as the PULP platforms have been chosen and/or evaluated by big companies like Google, IBM, micron, NXP, Dolphin Integr
  4 KB (661 words) - 08:38, 20 January 2021
• Wearables for Sports and Life Enhancement
  Wearables for Sports and Life Enhancement [[Category:Computer Architecture]]
  3 KB (381 words) - 14:17, 28 January 2023
• Physics is looking for PULP
  ...prove the quality of results, accelerate the rate at which data is sampled and allow new physical phenomena to be observed. ...planned to make this infrastructure openly available for other educational and research institutions.
  4 KB (497 words) - 16:50, 21 June 2018
• Analog Compute-in-Memory Accelerator Interface and Integration
  ...n-volatile devices, that can both perform logic and arithmetic operations, and function as memories, thus starting the in-memory computing (IMC) paradigm. ...nt state-of-the-art in terms of power efficiency (TOPS/W), retention time, and area scalability [2].
  3 KB (352 words) - 18:02, 16 December 2022
• Elliptic Curve Accelerator for zkSNARKs
  ...he correctness of the transaction: the input and output values add to zero and the sender actually owns the coins that he spends. ZCash would enable a dis ...wever: creating a zkSNARK requires a lot of computational power and energy and software implementations take 10s of seconds on a current processors. A lot
  5 KB (614 words) - 15:02, 4 March 2019
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  ...tories of athletes. Within the short duration of a ski-jump (< 10 seconds) and exposed to the conditions of nature (snow, wind, temperature) athletes must ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.
  6 KB (820 words) - 12:13, 23 July 2023
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  ...models the behavior of these networks. Individual network blocks are built and cascaded as single blackbox models using Python [https://scikit-rf.org/ sci ...system can be adapted in operation for a wide variety of transducer types and setups.
  5 KB (644 words) - 18:18, 21 July 2023
• NAND Flash Open Research Platform
  ...hat allows to directly interface to NAND flash ICs to study their behavior and argue about their security. ...rd able to interface with raw NAND flash chips. In particular, read, write and re-program them directly. This project would involve designing a PCB daught
  4 KB (551 words) - 11:06, 11 July 2019
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  ...d DHBTs, including their cut-off frequencies, breakdown voltages, vertical and lateral scalabilities, etc. ...Leveraging this simulation scheme, various DHBT systems could be simulated and potential design ameliorations could be proposed.
  4 KB (517 words) - 17:09, 16 September 2021
• NVDLA meets PULP
  [[File:nvdla_memory.png|right|NVDLA Memory System and High-Level Architecture]] ...on, competitor, accelerator, or encompassing framework to the PULP project and the accelerators/processors we have developed.
  6 KB (799 words) - 13:42, 10 November 2020
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  ...security and multimedia entertaining as well as biomedical devices as ECG and EEG wearable devices for health care applications are just few of these exa ...until it finally arrives to the server in the cloud which will process it and possibly give feedbacks to the users or to the microcontroller for closed-l
  7 KB (1,030 words) - 19:05, 29 January 2021
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
  ...high level semantically rich information out of raw data is deep learning, and in particular deep convolutional neural networks (CNNs). The task of infere ...design a PULP-based entire computation cluster around a set of deep, fast and low-power deep learning engines.
  7 KB (961 words) - 21:21, 29 January 2019
• Timing Channel Mitigations for RISC-V Cores
  ...hniques present in today's processors, combined with shared hardware state and timing channels that make it possible to leak information. ...act''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - '
  6 KB (915 words) - 18:16, 20 May 2020
• Developing a small portable neutron detector for detecting smuggled nuclear material
  ...preferably has an appropriate user interface, battery power for mobility, and data-logging/communication with a central location for analysis of data fro * Familiarization with the physics and current signal processing setup of the detector prototype
  5 KB (623 words) - 10:32, 5 November 2019
• ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
  ...ead to injuries. In clinical biomechanics, understanding changes in muscle and tendon properties is vital for creating effective treatment plans. ...particularly during fast movements like running, due to high acceleration and perspiration (falling off sensors), or when working with specific patient g
  6 KB (735 words) - 12:12, 23 July 2023
• Floating-Point Divide & Square Root Unit for Transprecision
  ...ly. In contrast to approximate computing where the precision of the entire system is reduced - often incurring loss in result quality - transprecision comput ...eresting for classic video and audio processing, but also machine learning and scientific computing workloads.
  8 KB (1,135 words) - 17:09, 29 July 2020
• Heroino: Design of the next CORE-V Microcontroller
  ...RE-V CV32E4 and CVA6 microprocessors, previously known as RI5CY and Ariane and originally developed at ETH Zurich. ...perience easy and standard, with industrial standard peripherals subsystem and software (as freeRTOS).
  9 KB (1,314 words) - 00:01, 7 February 2021
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
  ...ircuits after their fabrication, such technique would incur into low yield and high costs if applied to modern processes. ...pikes due to cosmic rays being captured by sequential elements, taking the system into a faulty state.
  6 KB (980 words) - 14:46, 2 June 2021
• Manycore System on FPGA (M/S/G)
  <!-- Manycore System on FPGA --> [[Category:Computer Architecture]]
  8 KB (1,319 words) - 10:41, 6 July 2021
• Hardware Acceleration
  ...nce sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be performed under a very tight power budget. Wit ...world performance as communication and data exchange between the processor and accelerator become major bottlenecks.
  7 KB (917 words) - 17:04, 24 November 2023
• Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
  ...w power, low cost, provably secure, high link budget (communication range) and automotive qualified wireless ranging device simply powered from a small co ...and carrier recovery approaches for signal acquisition of HRP UWB signals and clock offset compensation/tracking techniques for payload data decoding. Th
  5 KB (584 words) - 12:09, 29 October 2020
• Semi-Custom Digital VLSI for Processing-in-Memory
  ...o hit a “memory wall,” where most of the computations’ time, energy, and bandwidth is consumed by memory operations. This problem is further aggrava ...test, or migrate to other technology nodes, due to their analog component, and/or (ii) not applicable today, due to the use of immature semiconductor tech
  7 KB (882 words) - 14:33, 28 July 2021
• ASIC Implementation of Jammer Mitigation
  ...t research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms hav ...fficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology.
  5 KB (662 words) - 13:31, 10 May 2023
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  ...way to store volatile data, their potential for agressive voltage scaling and thus increasing the systems energy efficiency is limited. The goal of this [[File:Pulpissimo_archi.png|thumb|800px|PULPissimo SoC Architecture]]
  7 KB (1,032 words) - 15:31, 16 November 2020
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  ...e, due to their host processor capabilities, while having high performance and energy efficiency through their PMCAs. It's aim is to separate the function applied to the image (pipeline), and the sequence in which the algorithm is executed (schedule).
  5 KB (737 words) - 17:26, 2 November 2020
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
  <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> * VLSI I and II or equivalent: Understanding of at least one RTL language and ASIC design principles.
  11 KB (1,675 words) - 15:40, 15 March 2021
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
  * VLSI I or equivalent: Understanding of at least one RTL language and FPGA design principles. * Basic prior knowledge of embedded / bare-metal C and Assembly
  11 KB (1,617 words) - 23:59, 6 February 2021
• Peak-to-average power Reduction
  ...he tools to be learned in this project are numerical (convex) optimization and deep unfolding, a recent paradigm to tune algorithm parameters using deep l [[Category:Computer Architecture]]
  4 KB (513 words) - 14:16, 24 November 2021
• Software-Defined Paging in the Snitch Cluster (2-3S)
  [[Category:Computer Architecture]] ...le-precision FPUs and utilization-boosting extensions to maximize the area and energy spent on useful computation.
  4 KB (563 words) - 20:08, 15 February 2021
• DaCe on Snitch (M/1-3S)
  #Redirect [[LLVM and DaCe for Snitch (1-2S)]] [[Category:Computer Architecture]]
  2 KB (333 words) - 20:05, 15 February 2021
• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
  [[Category:Computer Architecture]] ...[1]. It is capable of booting Linux and it is widely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally
  3 KB (395 words) - 16:32, 15 November 2022
• IP-Based SoC Generation and Configuration (1-3S/B)
  [[Category:Computer Architecture]] ...evaluate their impact. Moving to more complex SoCs, top-level connectivity and parameterization become a major design issue:
  4 KB (617 words) - 10:19, 3 November 2023
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.
  8 KB (1,196 words) - 10:41, 6 July 2021
• Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
  ...(DM-MIMO) systems are channel charting [3], fingerprinting techniques [1], and triangulation/trilateration [4]. ...as the potential to significantly increase localization accuracy in indoor and rural scenarios, while avoiding the need of labeled training data.
  8 KB (931 words) - 17:27, 23 November 2021
• MemPool on HERO (1S)
  ...ile due to their host processor capabilities while having high performance and energy efficiency through their PMCAs. ...s designed for high energy efficiency for embedded applications with heavy and parallelizable workloads.
  6 KB (902 words) - 19:07, 20 January 2021
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  * 20% Synthesis and Backend [[Category:Computer Architecture]]
  8 KB (1,214 words) - 15:18, 9 July 2021
• ISA extensions in the Snitch Processor for Signal Processing (M)
  [[Category:Computer Architecture]] ...of parallelism and support domain-specific instructions to meet the timing and power constraints. One modern example of such an ISP is Google’s Pixel Vi
  9 KB (1,311 words) - 00:08, 13 March 2021
• Cell-Free mmWave Massive MIMO Communication
  ...rrier frequencies. Specifically, the combination of cell-free massive MIMO and millimeter wave (mmWave) communication promises to be the true enabler of t ...d the information is sent to the CPU, which performs detection, precoding, and power allocation. Instead of operating at sub-6-GHz, as conventional cellul
  7 KB (882 words) - 21:34, 13 July 2022
• Practical Reconfigurable Intelligent Surfaces (RIS)
  [[File:Image_RIS.png|400px|thumb|RIS aided wireless system.]] ...ies that improve energy efficiency are a big trend, so as to promote green and sustainable wireless systems.
  8 KB (1,011 words) - 12:25, 16 November 2023
• Snitch meets iCE40 (1-2S/B)
  * flexible logic architecture with up to 7680 LUTs and powerful DSP slices * simple footprint and only a minimal required supporting circuitry
  2 KB (365 words) - 20:03, 15 February 2021
• Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  ...end a matrix-vector product is nothing but a collection of multiplications and additions, these operations can be executed in different ways, for example, ...reate such architectures. This project requires knowledge of digital logic and VLSI implementation.
  5 KB (653 words) - 11:08, 12 November 2020
• Low-Resolution 5G Beamforming Codebook Design
  ...m with the capability to “beamform,” that is, to control the direction and shape of the beam pattern. Thanks to beamforming, the transmitter can focus ...ompute several potential solutions offline to form a fixed “codebook,” and then at run time, one only needs to choose the most adequate candidate solu
  6 KB (829 words) - 11:37, 12 November 2020
• Deep Unfolding of Iterative Optimization Algorithms
  ...ed using Deep Unfolding. The parameters to learn in this example are delta and tau.]] A great number of applications on signal processing, communications, and imaging, use iterative algorithms to gradually improve a first guess into a
  6 KB (748 words) - 13:57, 12 November 2020
• Matheus Cavalcante
  ...in 2018. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini. * Computer and System Architecture
  890 bytes (104 words) - 18:33, 8 December 2020
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  <!-- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform ( * 30% PCB testing and debugging
  11 KB (1,602 words) - 15:19, 9 July 2021
• Efficient Synchronization of Manycore Systems (M/1S)
  [[Category:Computer Architecture]] ...his coordination can limit the potential speedup offered by the multi-core system according to Amdahl’s law [[#ref-Hennessy2017|&#91;1&#93;]]. Efficient m
  12 KB (1,864 words) - 12:08, 29 August 2022
• Transforming MemPool into a CGRA (M)
  [[Category:Computer Architecture]] ...ISPs) which can exploit this high degree of parallelism to meet the timing and power constraints. One modern example of such an ISP is Google’s Pixel Vi
  13 KB (1,887 words) - 15:51, 17 November 2021
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
  [[Category:Computer Architecture]] ...get for FPGA emulation is the '''Genesys II''' board, and the mapping flow and auxiliary hardware environment provided by the Ariane maintainers offers a
  7 KB (1,122 words) - 15:21, 9 July 2021
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  * Interest in computer architecture [[Category:Computer Architecture]]
  8 KB (1,220 words) - 15:18, 9 July 2021
• LLVM and DaCe for Snitch (1-2S)
  <!-- LLVM and DaCe for Snitch (1-2S) --> [[Category:Computer Architecture]]
  11 KB (1,519 words) - 15:20, 9 July 2021
• Online Learning of User Features (1S)
  ...e user’s characteristics can considerably improve the performance of the system. We want to explore how the user-specific features can be exploited in orde ...ility of those features belonging to a certain class. A schematic of a KWS system can be seen in Figure 1.
  11 KB (1,610 words) - 11:00, 14 November 2022
• Huawei Research
  ...l and applied technology research, academic research cooperation projects, and strategic technical planning across our network of European R&D facilities. ...ironment that, like the best universities and research institutes, is open and conducive to such scientific work.
  6 KB (799 words) - 11:11, 1 August 2022
• Ibex: Tightly-Coupled Accelerators and ISA Extensions
  ...ions, Ibex can cover a variety of application scenarios ranging from small and efficient, 2-stage pipeline designs to beefier, 3-stage pipeline configurat ...[1], the work for this extension interface has been started at ETH Zürich and University of Bologna. In the meantime, a working group has been formed con
  6 KB (835 words) - 12:52, 27 April 2021
• Fast Simulation of Manycore Systems (1S)
  [[Category:Computer Architecture]] ...can efficiently communicate, making MemPool suitable for various workloads and easy to program.
  10 KB (1,434 words) - 17:20, 2 August 2021
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  <!-- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) --> [[Category:Computer Architecture]]
  11 KB (1,609 words) - 10:00, 30 June 2022
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  [[Category:Computer Architecture]] ...''decouples'' data movement from execution, hiding architectural latencies and maximizing bandwidth utilization.
  4 KB (557 words) - 16:14, 6 November 2022
• Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  <!-- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs --> [[Category:Computer Architecture]]
  3 KB (497 words) - 22:15, 23 November 2022
• Novel Methods for Jammer Mitigation
  ...uous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt ...cial, but these skills can also be acquired on the project itself. If time and interest permit, we will also investigate deep unfolding, an emerging parad
  6 KB (687 words) - 13:32, 10 May 2023
• Probing the limits of fake-quantised neural networks
  However, in many applications where latency and data privacy are essential constraints, it might be necessary to execute th QNNs have the double benefit of reducing models size and replacing the energy-costly floating-point arithmetic with the energy-effic
  5 KB (659 words) - 14:08, 15 February 2024
• Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
  ...ware-constrained devices, expanding the capabilities of a keyword spotting system. ...s are needed for rare diseases contexts, "where the incident rates are low and data sets at each single institution are too small". In this occasions, one
  12 KB (1,869 words) - 17:37, 1 September 2023
• VLSI Design of an Asynchronous LDPC Decoder
  ...automatically-generated layout of a simple processor implemented using ACT and fabricated in 65nm CMOS. ]] ...ns, asynchronous VLSI design was, up until now, not supported by EDA tools and, hence, enjoyed only limited use in practice.
  6 KB (725 words) - 17:36, 20 October 2021
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  [[Category:Computer Architecture]] ...lso decouples data movement from execution, hiding architectural latencies and maximizing bandwidth utilization.
  3 KB (431 words) - 16:13, 6 November 2022
• XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
  ...o hit a “memory wall,” where most of the computations’ time, energy, and bandwidth is consumed by memory operations. This problem is further aggrava ...test, or migrate to other technology nodes, due to their analog component, and/or (ii) not practical today, due to the use of an immature semiconductor te
  7 KB (933 words) - 19:29, 21 November 2021
• Integrating Hardware Accelerators into Snitch (1S)
  [[Category:Computer Architecture]] ...Us to minimize the control-to-compute ratio; it uses hardware loop buffers and stream semantic registers to achieve almost full FPU utilization.]]
  4 KB (567 words) - 13:57, 7 September 2022
• Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  [[Category:Computer Architecture]] ...tal circuit can be broken down into two main components: ''leakage power'' and ''dynamic power''.
  5 KB (688 words) - 13:51, 27 October 2022
• Non-blocking Algorithms in Real-Time Operating Systems
  [[Category:Computer Architecture]] [[Category:SW/HW Predictability and Security]]
  4 KB (508 words) - 18:59, 10 January 2022
• Adding Linux Support to our DMA Engine (1-2S/B)
  [[Category:Computer Architecture]] At IIS we are developing a modular and extensible high-performance direct memory access (DMA) engine. So far we ha
  2 KB (244 words) - 12:12, 21 June 2022
• Real-Time Embedded Systems
  ...ical instant''' at which these results are produced. In fact, a real-time system changes its state as a function of physical time. ...ster''), the ''real-time computer system'' (the ''computational cluster'') and the ''human operator'' (the ''operator cluster'').
  4 KB (518 words) - 09:54, 10 January 2022
• A Unified Compute Kernel Library for Snitch (1-2S)
  ...s of particular interest: it includes stream semantic registers (SSRs) [2] and the floating-point repetition (FREP) hardware loop, which together enable a ...y written in assembly, and use Snitch's extensions for maximum performance and efficiency.
  4 KB (554 words) - 09:49, 17 August 2022
• Implementing DSP Instructions in Banshee (1S)
  [[Category:Computer Architecture]] ...rchitectures and writing software for manycore systems is very challenging and requires the support of good simulation tools at various levels of abstract
  10 KB (1,428 words) - 13:31, 27 October 2022
• Streaming Integer Extensions for Snitch (M/1-2S)
  [[Category:Computer Architecture]] ...these lightweight extensions, the trade-off between control area overhead and FPU utilization is not an issue anymore for Snitch, as it is able to achiev
  6 KB (770 words) - 14:19, 15 September 2022
• Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  With the rise of machine learning, data mining, and 5G wireless communication, matrix-vector products have once again taken the ...rely on analog computation, and furthermore, PPAC can achieve better area- and energy-efficiency than traditional digital architectures that perform the s
  7 KB (804 words) - 19:45, 21 November 2021
• SCMI Support for Power Controller Subsystem
  [[Category:Computer Architecture]] [[Category:SW/HW Predictability and Security]]
  3 KB (467 words) - 13:55, 12 October 2022
• Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
  <!-- Peripheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) --> [[Category:SW/HW Predictability and Security]]
  8 KB (1,127 words) - 19:54, 1 March 2023

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