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- ...t role in this type of devices and in general in battery-operated embedded system. : Interest in Computer Architectures at system level2 KB (342 words) - 16:46, 11 February 2015
- ...o experienced students) comprises the implementation of such a measurement system. Possible approaches include a cross-correlating spectrum analyzer or the u2 KB (251 words) - 20:06, 17 February 2015
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- : Interest in Computer Architectures at system level ...arning would be beneficial (i.e. semester project or exam done in Wearable system I prof. Troester)3 KB (380 words) - 11:59, 28 July 2015
- ...hose in our prototype, and otherwise improve it by building a more compact system, adding communication capabilities to transmit suspicious cases to a remote [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]]8 KB (1,176 words) - 16:26, 30 October 2020
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2 KB (245 words) - 10:39, 6 November 2017
- [[File:origami-fpga-system.png|400px|thumb]] ...o finish the processing pipeline (activation, pooling), and completing the system by connecting a camera or loading a video stream and displaying the results3 KB (397 words) - 18:17, 29 August 2016
- [[Category:System Design]]4 KB (555 words) - 16:36, 23 May 2018
- ...al-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an i2 KB (340 words) - 10:39, 6 November 2017
- ..., televisions, pc among others. The main goal is to achieve an intelligent system that process the data from one or more sensors to understand the context an ...classification accuracy and energy efficiency and to further optimize the system.5 KB (669 words) - 17:22, 31 January 2018
- Using mixed-signal SoCs developed at IIS it is possible to integrate a system to conducting medical research. Despite low power consumption of the system the3 KB (366 words) - 13:05, 27 April 2018
- #REDIRECT [[System Analysis and VLSI Design of LTE NB-IoT Baseband Processing]]79 bytes (11 words) - 09:49, 19 October 2016
- #REDIRECT [[System Analysis and VLSI Design of NB-IoT Baseband Processing]]75 bytes (10 words) - 09:49, 19 October 2016
- #REDIRECT [[WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing]]84 bytes (9 words) - 15:33, 1 December 2016
- ...his project we would like to develop a concrete proof of concept low power System-on-Chip where (small) practical applications such as Spiking Convolutional ...connected. With regard to this, a higher-level synaptic array for the full System-on-Chip must be designed, taking into account even more strict area constra7 KB (1,000 words) - 12:22, 13 January 2017
- ...classification accuracy and energy efficiency and to further optimize the system. [[Category:System Design]]5 KB (703 words) - 17:21, 31 January 2018
- ...bedded image processing. The ambitious goal is to build a self-sustainable system that allows simple image processing to be implemented on-board the device. ...dy the required components for building a miniature ultra-low power camera system and develop a demonstration platform based on our ULP image sensor chip (de4 KB (602 words) - 10:45, 31 January 2023
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- ...he student he can be involved on the design of the IC, the layout, or at a system and application levler. The wake-up receiver should achieves power consumpt ...classification accuracy and energy efficiency and to further optimize the system.5 KB (686 words) - 11:54, 2 February 2018
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4 KB (605 words) - 16:35, 20 February 2018
- ...hanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level d ...dictates battery size, the most critical factor in any volume-constrained system.4 KB (597 words) - 16:57, 12 July 2022
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- ..., non-invasive method to measure kidney performance via an external sensor system to avoid the use of urinary catheters for this subgroup of patients, thereb ...classification accuracy, and energy efficiency and to further optimize the system. The work includes the modeling and design of a suited impedance sensor, it6 KB (857 words) - 15:37, 10 November 2020
- ...roject focusses on the development of an unobtrusive multisensory embedded system to assist coaches to better quantify jumping trajectories of athletes. With ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.6 KB (820 words) - 12:13, 23 July 2023
- ...pikes due to cosmic rays being captured by sequential elements, taking the system into a faulty state.6 KB (980 words) - 14:46, 2 June 2021
- #REDIRECT [[PULP in space - Fault Tolerant PULP System for Critical Space Applications]]88 bytes (13 words) - 13:10, 9 August 2019
- ...rphic intelligence using their processor to build a whole working embedded system. The student will deal with both hardware and software building a prototype * Motivation to build and test a real system5 KB (692 words) - 15:45, 10 November 2020
- ...ock diagram, which involves both the programming of a Low power FPGA and a System on Chip with ARM cortex-M4F and Bluetooth low energy 5.0. The project is qu * Motivation to build and test a real system4 KB (526 words) - 15:48, 10 November 2020
- <!-- Manycore System on FPGA --> At ETH, we are developing our own many-core system called MemPool [1]. It boasts 256 lightweight 32-bit Snitch cores developed8 KB (1,319 words) - 10:41, 6 July 2021
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- ...s is to have Halide programmed image processing kernels running on an HERO system implemented on an FPGA.5 KB (737 words) - 17:26, 2 November 2020
- <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> One of the most tedious and error-prone steps is assembling a peripheral system with the required and desired IO; this usually involves adapting existing p11 KB (1,675 words) - 15:40, 15 March 2021
- #REDIRECT [[Implementation of a Heterogeneous System for Image Processing on an FPGA (S)]]90 bytes (13 words) - 17:26, 2 November 2020
- ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.8 KB (1,196 words) - 10:41, 6 July 2021
- #REDIRECT [[Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)]]82 bytes (11 words) - 17:40, 2 November 2020
- ...ludes them from being used in a portable system. Furthermore, surveillance system typically do not come with any localized intelligence, so their recorded da In this project, a novel, distributed and energy-efficient surveillance system will be brought up and optimized by the student.3 KB (433 words) - 15:36, 4 August 2022
- <!-- Peripheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) --> ...unities are limited due to the necessity to retain major parts of the main system memory due to the use of static random access memory (SRAM) for code execut8 KB (1,127 words) - 19:54, 1 March 2023
- ...ormation on the structure of musculoskeletal tissues, organs, and vascular system. The velocity of liquid flows (as for arteries and veins) can be measured b Preliminary results of custom syringe pump system:3 KB (363 words) - 17:18, 3 May 2024
- At ETH, we developed our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme ...d to integrate an FLL, a boot ROM, and a JTAG to access and initialize the system. While there are many IPs and know-how at IIS for that, this is also highly8 KB (1,239 words) - 12:36, 29 January 2024
- ...ed Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1M) --> ...ople.ee.ethz.ch/~janniss/projects/Maddness_system_integration.pdf Maddness System Intergration]6 KB (846 words) - 16:50, 3 November 2022
- <!-- AXI-based Network on Chip (NoC) system --> ...ould be to build a system with a mesh NoC and a couple of cores and do the system integration for a potential tapeout. For the verification, low-level softwa2 KB (252 words) - 14:43, 23 October 2023
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- ...n technique is to combine multiple instances of a core to a ''multi-core'' system. This technique introduces a new challenge: Each core keeps its own copy of ...ane cores. Throughout this project, the feasibility and performance of the system shall be evaluated.2 KB (260 words) - 16:41, 15 November 2022
- ...Qubits will be read-out at the same time. For discrete Qubits, the readout system usually works at the sub-1 GHz frequency range. However, for a compact foot2 KB (372 words) - 10:32, 14 February 2023
- ...t needs to be accessed and monitored calls for a high-speed FPGA/GPU based system with a compact, and incubator-compatible hardware design. [[Image:Hangxing FPGA.png|800px| System Overview]]6 KB (720 words) - 16:27, 27 September 2023
- ...n a limited power budget require a novel approach across the entire stack, system-level design, and optimization. ...red offchip]] [[File:DistributedOnSensor.png|500px|thumb|right|Distributed System -> Only Region of Interest section of image is transferred offchip]]4 KB (577 words) - 18:28, 4 October 2023
Page text matches
- * [[Noise Figure Measurement for Cryogenic System]] * [[A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities]]5 KB (537 words) - 15:22, 23 February 2024
- ...er, there is a lot of functionality which will never be used in the target system and it is therefore not necessary to maintain all this functionality. Remov ...Adding User I/O to the Processor''': If the processor is not embedded in a system, it is like a blackbox which computes something and stores the result in th10 KB (1,669 words) - 19:01, 30 January 2014
- ...ilog code, is the '''emacs''' editor, as it has a really advanced VHDL and System Verilog mode. Because of this, you should get comfortable with the idea of841 bytes (137 words) - 14:42, 16 January 2014
- dynamically modify the timing constrains aiming to tolerate at system level reliable computing system in nano-meter technology operating in3 KB (409 words) - 10:52, 27 March 2014
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]4 KB (397 words) - 15:44, 14 February 2023
- ...-process this data in order to compact it for the transport to the imaging system. A special challenge pose the high-speed output pin drivers. In case of int ...o reduce the incidental data rates between the sensor head and the backend system, and second, new beamforming strategies to minimize the computational burde4 KB (614 words) - 20:10, 17 February 2015
- TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na1 KB (206 words) - 14:07, 9 February 2015
- TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na1 KB (160 words) - 11:17, 23 September 2016
- ...le or strechable materials to form wearable and conformable devices. These system are often composed of various flexible, bendable but also small ridgid comp4 KB (444 words) - 12:43, 23 July 2023
- ...ure in such a way that later studies will allow '''ML-based control of the system'''. ...architecture is to be designed in such a way that ML-based control of the system is possible.6 KB (741 words) - 18:14, 21 July 2023
- TD-SCDMA is a 3GPP standard that combines an advanced TDMA/TDD system with an adaptive CDMA component operating in a synchronous mode. Its TDD na1 KB (158 words) - 11:17, 23 September 2016
- TD-HSPA is a 3GPP standard that combines an advanced TDMA/TDD system with an adap- MLSD computation for a system with such dimensions practically impossible given the current5 KB (684 words) - 10:43, 6 November 2017
- ...ject, you will assess the effect of carrier aggregation in an LTE-Advanced system. You will start by implementing a MATLAB framework to simulate the LTE-Adva3 KB (405 words) - 16:13, 29 December 2016
- ...he chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emer ...ring the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can be tested using a proto3 KB (382 words) - 20:00, 26 September 2017
- Forward error correction is a crucial part in any communication system, since it enables reliable transmission over unreliable channels. In mobile3 KB (508 words) - 11:12, 14 April 2016
- ...ill form the standard chip to chip communication standard for the [[PULP]] system.3 KB (492 words) - 12:34, 7 November 2017
- applications for this system is in real-time video applications, expecially system, improving the energy efficiency of the system. The accelerator will3 KB (407 words) - 10:57, 5 November 2019
- The IIS 2G testbed has no operating system (OS) running on [4] FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems3 KB (421 words) - 10:40, 6 November 2017
- ...tp://www.freertos.org/ FreeRTOS - Market leading RTOS (Real Time Operating System) for embedded systems with Internet of Things extensions], June 2015.2 KB (273 words) - 11:30, 24 February 2017
- ...data over a wireless link. Some of these system even include an actuation system, which reacts depending on the captured data. ...nnected and operate and act collaboratively it is called a 'cyper-physical system' (CPS).3 KB (418 words) - 11:24, 10 November 2017
- ...tion of the FPUs and therefore reduce the overall power consumption of the system. Sharing FPUs allows to employ several different units, which can be either ...nd is a promising approach to further improve the energy efficiency of the system. One way to approximate FP-operations is to use Newton's method to compute3 KB (377 words) - 10:58, 21 February 2018
- ...egory:Qcrypt|QCRYPT]] was the development of the 100 Gbit/s link encryptor system with a variety of optical interfaces on the plain-text side and a 100 Gbit ...main focus lay on the development of a second version of the PCB for this system. The layer stackup was modified to enhance the high-frequency quality of th2 KB (359 words) - 20:06, 17 February 2015
- ''2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)'', Santa Cruz, California, USA, 7-10 Oct 20123 KB (392 words) - 12:25, 26 March 2015
- ...erent mobile platforms, most productions are captured with one acquisition system at fixed parameters. Examples for content adaption algorithms are content-a ...ons and VLSI Implementations", ''VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, volume 418 of IFIP Advances in Information and Communicatio4 KB (520 words) - 16:04, 13 May 2015
- ...IC/FPGA system which implements the first three steps of this process. Our system is able to extract SKB features from one 720p video stream in real time (303 KB (487 words) - 15:57, 13 May 2015
- ...ing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparen1 KB (193 words) - 15:39, 3 March 2020
- ...the image is being acquired and forward this information to a larger host system for further processing. ...algorithm steps directly ion hardware and interface with the host computer system.3 KB (357 words) - 18:53, 6 December 2014
- ...bits. Such data converters are intended to be embedded in a mostly digital system, and this legitimates the adoption of ultra-scaled CMOS technologies from w2 KB (277 words) - 17:28, 29 January 2014
- Although the wireless and battery-powered nature of this system reduces the impact of mains interference, its amplitude might nonetheless b ...ed by an off-the-shelf mobile phone battery which is sufficient to run the system for several hours - the battery life-time is mainly limited by the Bluetoot2 KB (280 words) - 10:54, 10 March 2015
- his PhD thesis entitled "An Evolved EDGE System on Chip for the Cellular894 bytes (115 words) - 17:17, 30 November 2021
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (597 words) - 12:56, 4 December 2021
- ...upper layers of the OsmocomBB GSM protocol stack. The functionality of the system is verified with a testbed comprising a base station and a receiver board w3 KB (360 words) - 14:14, 27 May 2015
- ...ssor and the unit where RLC blocks are processed for IR is attached to the system processor. The decoding of the RLC blocks takes place on a PHY Digital Sign3 KB (397 words) - 14:12, 27 May 2015
- ...ons such as those in the time-duplexing high speed packet access (TD-HSPA) system.2 KB (266 words) - 10:43, 9 February 2015
- ...terms of parallelism, performances and robustness. One has to revisit the system design in terms of usage of hardware accelerators, heterogeneous or homogen4 KB (568 words) - 12:48, 9 February 2015
- ...communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates.]] ...Q operation that is critical for the average throughput performance of the system.2 KB (343 words) - 13:56, 9 February 2015
- ...channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations.]] ...ion-specific cost functions) substantially increases the robustness of the system to unreliable memory operation, compared to the data representations most c3 KB (352 words) - 13:56, 9 February 2015
- ...t role in this type of devices and in general in battery-operated embedded system. : Interest in Computer Architectures at system level2 KB (342 words) - 16:46, 11 February 2015
- ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.3 KB (487 words) - 12:02, 27 January 2016
- ...a low power radio wake up receiver can reduce the power consumption of the system while still keeping its response time low. Another role of the wake-up radi ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe4 KB (613 words) - 19:54, 9 February 2015
- ...ices while still keeping its wake up time low. Another role of the wake-up system is that based on "intelligence" to select a specific device which has to be ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe3 KB (515 words) - 19:55, 9 February 2015
- [[File:FeatureExtractionSystem.jpg|thumb|500px|Current feature extraction system.]] ...rrently used in the video analysis part of a more complex video processing system which performs [[Real-Time_Stereo_to_Multiview_Conversion|automatic multiv3 KB (373 words) - 11:51, 19 August 2017
- ...o experienced students) comprises the implementation of such a measurement system. Possible approaches include a cross-correlating spectrum analyzer or the u2 KB (251 words) - 20:06, 17 February 2015
- ...uld be to evaluate and integrate this camera into a working scene labeling system [[http://dl.acm.org/citation.cfm?id=2744788 paper]] and would be very diver * create a system from the individual parts (build a case/box mounting the cameras, dev board6 KB (941 words) - 11:29, 5 February 2016
- ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence5 KB (784 words) - 14:50, 30 November 2016
- [[Category:Biomedical System on Chips]]2 KB (278 words) - 16:57, 12 July 2022
- [[Category:System Design]]2 KB (348 words) - 20:01, 26 September 2017
- * Designing the system architecture * Defining the circuit using hardware description languages (HDL) such as (System Verilog or VHDL) for [[:Category:Digital|digital projects]], and schematic1 KB (165 words) - 19:52, 10 February 2015
- * Understand the different available peripherals on your system board * Run your system on the development board and collect the results.1,020 bytes (132 words) - 19:50, 10 February 2015
- ...will be able to control the accelerator from the command line of the Linux system. :[3] [http://www.arm.com/products/system-ip/amba/amba-open-specifications.php ARM AMBA Specification]2 KB (236 words) - 09:46, 12 October 2017
- [[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]] * [http://asic.ethz.ch/2020/Thestral.html Thestral] Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed t10 KB (1,563 words) - 10:09, 19 August 2022
- [[Category:System Design]]3 KB (449 words) - 12:12, 4 November 2019
- ...r OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can co : For low power operations, we would like to shutdown most of the system including the processor, and wait until there is an event that requires the4 KB (667 words) - 15:23, 23 December 2016
- In recent years reseach works shows that thermal evolution of a multicore system can be effectively modelled with linear state-space representation enabling ...will then be part of a larger system and be part of the thermal management system. In this project the goal is to implement a novel MPC algorithm in hardware3 KB (456 words) - 08:35, 20 January 2021
- ..., R.N. Challa, and H.A. Mahmoud. Frequency Scan Method for Determining the System Center Frequency for LTE TDD, September 6 2013. WO Patent App. PCT/US2013/02 KB (350 words) - 17:56, 14 April 2016
- ====[[Biomedical System on Chips|Biomedical System on Chips]]==== ...f wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless transmis3 KB (369 words) - 18:11, 1 March 2023
- ...method by implementing our system.. Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe : Interest in Computer Architectures at system level3 KB (378 words) - 19:56, 9 February 2015
- Reliability (R(t)) is the probability that a given system does not fail before time t. It is becoming a major concern in modern multi ...bile]] [[Category:Temperature]] [[Category:Dynamic Management]] [[Category:System Design]]4 KB (573 words) - 17:24, 9 February 2015
- ...s an heterogeneous thermal profile which is highly dependent on the actual system usage. As a matter of fact today and future mobile devices are thermally li ...thermal model can be directly identified from the target device by mean of system identification and self-calibrating routines.3 KB (452 words) - 11:03, 10 February 2015
- [[Category:System Design]]3 KB (408 words) - 13:17, 5 February 2016
- ...stem was proposed alongside the release-8 of the Long Term Evolution (LTE) system for the fourth generation (4G) of mobile communication. While the air inter ...tionality of a standard-compliant physical layer of a mobile communication system. Possibly, the student can also investigate and analyze an interesting perf1 KB (159 words) - 11:16, 23 September 2016
- [1] ''Cellular system support for ultra-low complexity and low throughput Internet of Things (CIo3 KB (384 words) - 16:41, 17 July 2016
- ...E transceiver [2] will be used. You will start with your design by doing a system analysis on the required building blocks (Synchronization, FFT, Symbol dete [[Category:System Design]]3 KB (335 words) - 14:20, 4 November 2019
- : Matlab, C++, VHDL or System Verilog2 KB (351 words) - 13:09, 2 November 2015
- : Matlab, C++, VHDL or System Verilog2 KB (328 words) - 12:38, 1 June 2017
- ...er, a careful design of each regulator is extremely important. A PCB-based system, containing of-the-shelf converter chips where available, and discrete-comp [[Category:System Design]]3 KB (438 words) - 18:06, 3 February 2015
- ...be mapped to both cores. This results in a lower active time, allowing the system to enter a low-power sleep mode, and reduce the total energy consumption.3 KB (431 words) - 18:04, 28 January 2017
- [[Category:System Design]]4 KB (589 words) - 10:14, 3 August 2018
- : Interest in Computer Architectures at system level : Wearable system I (prof. Troester lectures)2 KB (319 words) - 16:24, 30 October 2020
- [[File:mvSystem.jpg|thumb|600px|a) Multiview system in action and b) closeup of the hardware prototype.]] Ideally, a 3D display system should not require the users to3 KB (509 words) - 09:09, 23 October 2015
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]7 KB (811 words) - 15:21, 23 February 2024
- ...event-driven simulator designed for simulating IoT processors and complex system-on-chips (SoCs). It plays a crucial role in enabling agile design space exp * Experience with System Verilog is recommended but not strictly necessary4 KB (520 words) - 15:15, 4 December 2023
- ...k, Nitin Mangalvedhe, Amitava Ghosh, and Benny Vejlgaard. Narrowband LTE-M system for M2M communication. 2014.4 KB (561 words) - 10:43, 6 November 2017
- is indispensable. Ideally, System-on-a-Chip (SoC) or System-in-a-Package (SiP) modems such as [1] are7 KB (1,105 words) - 20:02, 26 September 2017
- [[Category:Digital]] [[Category:System Design]]5 KB (707 words) - 11:22, 5 February 2016
- [[Category:System Design]]1 KB (169 words) - 16:42, 9 December 2015
- ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...L1 scratchpad memory, and the shared main memory to optimally exploit the system's memory hierarchy and to achieve high performance.5 KB (716 words) - 13:43, 29 November 2019
- ...e piezoelectric elements in the transducer head are connected to a backend system over a large cable containing hundreds of small coaxial cables. This is sho In order to do so, the entire analog frontend of the ultrasound system needs to be integrated into the transducer head and a digital link needs to3 KB (378 words) - 11:52, 10 January 2017
- ...tation of an entire scene labeling network. In order to keep the developed system flexible in terms of the convolutional neural network that is applied as we ...rt software blocks to programmable logic and design an entire hetergeneous system using with software, FPGA fabric and hardwired interfaces.8 KB (1,197 words) - 18:18, 29 August 2016
- [[Category:System Design]]3 KB (420 words) - 11:22, 14 April 2016
- ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e This system design project requires work to be done at several layers of abstraction. M4 KB (585 words) - 17:57, 7 November 2017
- ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e : VHDL/System Verilog, C4 KB (554 words) - 17:57, 7 November 2017
- ...ment of novel zero-power sensors that act as a trigger for the rest of the system when an important event is detected and consume zero-power between two dete ...classification accuracy and energy efficiency and to further optimize the system.6 KB (774 words) - 08:36, 23 November 2022
- [[Category:System Design]] [[Category:System Design]]4 KB (471 words) - 11:13, 3 May 2018
- ...we have implemented and fabricated an 8-channel biosignal acquisition SoC (System-on-Chip) [http://asic.ee.ethz.ch/2014/CerebroV4.0_Homer.html] including ana2 KB (353 words) - 08:35, 20 January 2021
- [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Luk [[Category:Digital]] [[Category:System Design]]4 KB (563 words) - 11:29, 5 February 2016
- ...classification accuracy and energy efficiency and to further optimize the system. : Interest in Computer Architectures at system level3 KB (448 words) - 11:59, 28 July 2015
- : Interest in Computer Architectures at system level ...arning would be beneficial (i.e. semester project or exam done in Wearable system I prof. Troester)3 KB (380 words) - 11:59, 28 July 2015
- [[Category:System Design]]4 KB (507 words) - 12:11, 16 February 2016
- ...otal power spent for event detection, we propose an alternative, two-stage system architecture consisting of: 1. "wake-up sensing" (WUS) circuit, and 2. main [[Category:System Design]]7 KB (895 words) - 17:02, 28 July 2017
- ...hose in our prototype, and otherwise improve it by building a more compact system, adding communication capabilities to transmit suspicious cases to a remote [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]]8 KB (1,176 words) - 16:26, 30 October 2020
- ...by canceling self-induced motion blur. The VOR is driven by the vestibular system and induces short-latency eye movements in the opposite direction to the he2 KB (376 words) - 14:43, 29 July 2015
- ...l-diversity streams have been introduced with the Evolved EDGE 2G cellular system [1], the recent EC-GSM-IoT standard achieves up to 20 dB coverage extension3 KB (418 words) - 10:39, 6 November 2017
- ...ration of the communication portion of the node is indispensable. Ideally, System-on-a-Chip (SoC) modems are used.2 KB (299 words) - 17:58, 14 April 2016
- [[Category:System Design]]3 KB (390 words) - 11:59, 20 June 2016
- [[Category:System Design]]4 KB (593 words) - 14:57, 30 November 2016
- ...lly, the goal is to attach the developed accelerator to the ARM processing system on the Xilinx Zynq platform, and establish the corresponding software inter : Matlab, C++, VHDL or System Verilog4 KB (542 words) - 12:39, 1 June 2017
- ...stablished method to save power in circuit parts currently not in use in a system on chip (SoC). In contrast to clock gating, where the clock signal is disab2 KB (364 words) - 09:34, 25 July 2017
- Memories are central building blocks of any processing system, in fact most of the performance of a modern processor is determined by its5 KB (769 words) - 15:54, 23 May 2018
- [[Category:System Design]]2 KB (340 words) - 11:55, 21 August 2018
- [[File:origami-fpga-system.png|400px|thumb]] ...o finish the processing pipeline (activation, pooling), and completing the system by connecting a camera or loading a video stream and displaying the results3 KB (397 words) - 18:17, 29 August 2016
- <!--[[File:origami-fpga-system.png|400px|thumb]] --> [[Category:Hot]] [[Category:Digital]] [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Mas2 KB (285 words) - 18:16, 29 August 2016
- [1] 3GPP. Cellular System Support for Ultra Low Complexity and Low Throughput Internet of Things. htt4 KB (582 words) - 20:00, 26 September 2017
- [[File:iPMU.png|600px|thumb|right|iPMU within a Generalized System]] ...ilable energy for the system and learn the energy consumption of different system tasks. Moreover, the iPMU should profile the available power input from the2 KB (292 words) - 11:40, 2 June 2021
- ...such as battery or supercapacitor for future use. A correctly dimensioned system will guarantee the node’s operation during periods of energy unavailabili3 KB (366 words) - 18:04, 28 January 2017
- ...rs. In our lab, we have developed a energy management unit, which allows a system designer to provide energy guarantees solely from volatile energy harvestin [[Category:System Design]]3 KB (413 words) - 15:21, 28 January 2016
- [[Category:Software]] [[Category:System]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2016]] * Interest in computer vision and system engineering5 KB (747 words) - 18:04, 29 August 2016
- [[Category:System Design]]3 KB (426 words) - 11:41, 21 July 2017
- : VHDL/System Verilog knowledge3 KB (377 words) - 10:25, 5 November 2019
- ...ultra low power consumption are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is : VHDL/System Verilog knowledge3 KB (384 words) - 17:24, 21 August 2019
- ...wn approach to improve the overall performance of a wireless communication system. The underlying principle is to feed back soft information from the channel [[Category:System Design]]3 KB (450 words) - 11:43, 13 November 2018
- ...w evaluation platform based on the Juno ARM Development Platform [3]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F : VHDL/System Verilog, C5 KB (711 words) - 10:27, 5 November 2019
- [[Category:System Design]]3 KB (402 words) - 15:31, 13 April 2016
- [[Category:System Design]]3 KB (418 words) - 14:01, 13 November 2020
- Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power c *Control system DMA to save/restore L1 data memory2 KB (236 words) - 08:35, 20 January 2021
- ...o maintain as much as possible the general purpouse phylosofy of the whole system.2 KB (237 words) - 10:27, 5 November 2019
- [[Category:System Design]]4 KB (555 words) - 16:36, 23 May 2018
- ...tion of the FPUs and therefore reduce the overall power consumption of the system. We have already designed a FPU unit with support for FP-additions, FP-subt ...dware efficient architecture for a fused multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.2 KB (346 words) - 10:26, 5 November 2019
- : Knowledge of a hardware design language such as (System)Verilog or VHDL. [[Category:System Design]]4 KB (522 words) - 13:38, 10 November 2020
- [[Category:System Design]]3 KB (403 words) - 20:45, 9 August 2016
- : 20% VHDL/System Verilog, FPGA Design : VHDL/System Verilog, C5 KB (712 words) - 17:57, 7 November 2017
- ...ngs of arbitrary size, independent of the page size of the Linux operating system running on the host CPU. In a student project [4], a second, set-associativ ...and give access to it to user-space applications through, e.g., an mmap() system call. Ideally, all data shared with the accelerator is placed in this secti6 KB (866 words) - 13:43, 29 November 2019
- ...al-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an i2 KB (340 words) - 10:39, 6 November 2017
- [4] Scaramuzza et al., Vision-Controlled Micro Flying Robots: From System Design to Autonomous Navigation and Mapping in GPS-Denied Environments, htt6 KB (828 words) - 16:26, 20 February 2018
- ...nd obtrusive storage element. One of the biggest challenges in batteryless system design is the cold start phase, where the harvesting circuit needs to self- Finally a full system which include the energy harvesting and a sensor (a ultra low power camera3 KB (485 words) - 17:46, 10 August 2016
- ...setup a basic ultrasound simulation for a moderate (1024) channel count 3D system based on existing scripts. Then he has to assess several tracking algorithm [[Category:System Design]]2 KB (253 words) - 20:52, 12 November 2020
- [[Category:System Design]]2 KB (320 words) - 10:56, 10 January 2017
- ...nd eventually supply it with energy harvesting from the human body. A full system will be developed that will incldue the processing part, the wireless inter [[Category:System Design]]4 KB (631 words) - 11:39, 21 July 2017
- ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.4 KB (571 words) - 21:42, 30 July 2018
- ..., televisions, pc among others. The main goal is to achieve an intelligent system that process the data from one or more sensors to understand the context an ...classification accuracy and energy efficiency and to further optimize the system.5 KB (669 words) - 17:22, 31 January 2018
- ...s kind of communication. The project will also focus on how make the whole system self-sustaining using RF energy harvesting or other kind of energy harvesti [[Category:System Design]]4 KB (576 words) - 16:58, 28 July 2017
- ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors interconnected by wireless links. We want ...e power consumption reduction, reliability, functionality and optimize the system.5 KB (617 words) - 16:22, 27 February 2018
- ...ard-FPGA and to implement the control sidechannel interface to the backend system (a PC in our case). * Design an interface/API such that the firmware can talk to the backend system (UART based)3 KB (458 words) - 20:51, 12 November 2020
- Using mixed-signal SoCs developed at IIS it is possible to integrate a system to conducting medical research. Despite low power consumption of the system the3 KB (366 words) - 13:05, 27 April 2018
- <!--[[File:origami-fpga-system.png|400px|thumb]] --> [[Category:Hot]] [[Category:Digital]] [[Category:System Design]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category3 KB (362 words) - 16:25, 30 October 2020
- ...nodes. Computing nodes based on ARM SoCs are facing the market, as well as system based on the IBM power architecture. To create more market opportunities IB *Good computer architecture and real-time system background.3 KB (462 words) - 15:57, 9 September 2016
- *Knowledge of the Linux Operating System architecture3 KB (417 words) - 15:55, 9 September 2016
- ...ansport this data-rate efficiently from the head to the backend processing system, we use a optical high-speed link. ...d software IPs. Using these IPs allows to build rather easily very complex system. You will be extensively working with the Xilinx Vivado Tool.3 KB (409 words) - 10:55, 10 January 2017
- ...on the power consumption of those circuits that are always on, like e.g. a system clock. So this topic has seen a lot of attention in recent years. The aim o2 KB (368 words) - 18:58, 19 December 2016
- ...nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student, for a semester thesis the work w : 20% System Simulation (Matlab/Simulink)3 KB (375 words) - 17:46, 2 May 2017
- ...nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student. : 20% System Simulation (Matlab/Simulink)3 KB (358 words) - 11:40, 20 August 2021
- ...esis]] [[Category:2016]] [[Category:Barandre]][[Category:PULP]][[Category:System Design]] ...nts the software control loop which maximizes the energy efficiency of the system dynamically tracking the PVT variations3 KB (348 words) - 15:31, 13 September 2016
- ...ors that are always on are usually slow and exhibit too much noise. When a system clock is available dynamic comparators are an attractive alternative, as th3 KB (362 words) - 17:35, 21 December 2017
- Mixed-signal system-on-chips (SoCs) often consist of various independent subsystems (e.g., diff3 KB (389 words) - 11:20, 14 September 2016
- The student will design and implement an ultra low power system testing the performances of the whole system by using a commercial RF4 KB (609 words) - 11:38, 21 July 2017
- ...main goal of the design is to optimize the power consumption to allow the system to life several months without change the battery. THe project will be done : Interest in Computer Architectures at system level4 KB (502 words) - 11:38, 21 July 2017
- system.6 KB (900 words) - 16:58, 7 May 2018
- As the key for wireless transceiver system, Phase-locked loop (PLL) is a general solution for frequency synthesize. In4 KB (514 words) - 15:51, 20 August 2021
- #REDIRECT [[System Analysis and VLSI Design of LTE NB-IoT Baseband Processing]]79 bytes (11 words) - 09:49, 19 October 2016
- #REDIRECT [[System Analysis and VLSI Design of NB-IoT Baseband Processing]]75 bytes (10 words) - 09:49, 19 October 2016
- [[Category:System Design]]2 KB (259 words) - 11:34, 10 November 2017
- [[Category:System Software]]2 KB (352 words) - 11:51, 21 August 2018
- ...(IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-sensor computi ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence9 KB (1,427 words) - 18:36, 5 September 2019
- ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne6 KB (909 words) - 19:50, 30 May 2017
- #REDIRECT [[WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing]]84 bytes (9 words) - 15:33, 1 December 2016
- ...in which the signal is digitized directly in the probe and sent to the US system through an optical fiber. This digitization enables a higher flexibility fo [[Category:System Design]]4 KB (521 words) - 10:37, 26 October 2021
- [[File:Ultralight.jpg|thumb|400px|Current Prototype System]] * Programming of software functions: Microcontroller Programming / Processing system programming (C/C++/CUDA)2 KB (254 words) - 14:14, 31 October 2020
- ...head. The beamformer is the core processing unit in any ultrasound imaging system as it produces the image from the raw sensor data. Similar to other handhel ...figures the beamformer based on real-time temperature sensor data from the system.3 KB (374 words) - 20:50, 12 November 2020
- ...rly defined algorithmic problem and actually test the result in a complete system with real world data.2 KB (295 words) - 11:27, 6 November 2017
- ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne6 KB (920 words) - 16:33, 3 October 2019
- ...his project we would like to develop a concrete proof of concept low power System-on-Chip where (small) practical applications such as Spiking Convolutional ...connected. With regard to this, a higher-level synaptic array for the full System-on-Chip must be designed, taking into account even more strict area constra7 KB (1,000 words) - 12:22, 13 January 2017
- ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne5 KB (794 words) - 13:19, 13 January 2017
- * Familiarity with embedded system programming in C. [3] Altium Design System http://www.altium.com/6 KB (875 words) - 11:06, 23 February 2018
- ...classification accuracy and energy efficiency and to further optimize the system. [[Category:System Design]]5 KB (703 words) - 17:21, 31 January 2018
- [[Category:System Design]]3 KB (392 words) - 14:17, 5 April 2022
- Within this project, you will built such a system. It should be able to quickly and robustly scan the labels and provide the ...care, image processing and interface design. A successful implement of the system will improve patient care by reducing the workload on the intensive care st2 KB (315 words) - 13:00, 22 February 2017
- [[Category:System Design]]3 KB (462 words) - 13:54, 13 November 2020
- ...L implementation of HD computing for an EMG-based hand gesture recognition system with fast learning using much lower power than ever before. [[Category:System Design]]4 KB (467 words) - 13:38, 10 November 2020
- * Knowledge of a hardware design language: e.g. (System)Verilog or VHDL6 KB (842 words) - 08:37, 20 January 2021
- ...ry purpose of this project is to contribute to the ''Ergo'' deep inference System-on-Chip by designing HW/SW techniques for the acceleration of aggressively ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended6 KB (949 words) - 13:41, 10 November 2020
- ...f hardware design and computer architecture - having followed the Advanced System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics [https://arxi6 KB (916 words) - 15:50, 7 December 2018
- The prototype system on which the source localization application will be implemented is constit ...of sound waves, at the two ears. Similarly to what is done by our auditory system to detect the azimuthal direction of a sound, by looking at the time differ7 KB (1,025 words) - 19:52, 30 May 2017
- [[Category:System Design]]4 KB (546 words) - 11:33, 17 April 2020
- [[Category:System Design]]3 KB (372 words) - 20:22, 1 April 2019
- ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx7 KB (1,001 words) - 10:43, 26 June 2017
- [[Category:System Design]]3 KB (401 words) - 19:08, 29 January 2021
- ...e HDL (hardware description language) of your choice (for example VHDL or (System)-Verilog) as thought in VLSI I and II ...lel Computing Systems for Data Analytics class (formerly known as Advanced System on a Chip)5 KB (729 words) - 11:27, 11 December 2018
- [[File:Hyperdimensional-Solar-System.jpg|thumb]] [[Category:System Design]]3 KB (366 words) - 15:39, 10 November 2020
- ...he existing LightProbe prototype with a Wireless LAN module to provide the system with a low-rate (Mbit/s) interface to connect directly with a mobile phone ...ples are provided) and write the required scripts/program on the receiving system (can be a laptop) to capture the sent data.2 KB (324 words) - 16:59, 16 September 2022
- * VHDL or (System)-Verilog knowledge, VLSI I & II4 KB (603 words) - 09:37, 10 July 2018
- both dramatically simplifying the programmability of such a heterogeneous system. ...aluation platform [5] based on the Juno ARM Development Platform [6]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F6 KB (805 words) - 12:17, 22 January 2018
- both dramatically simplifying the programmability of such a heterogeneous system. ...aluation platform [5] based on the Juno ARM Development Platform [6]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F6 KB (801 words) - 15:05, 23 August 2018
- initiatives such as the Heterogeneous System Architecture foundation (HSA) are access to system memory from both sides, eliminating the need for explicit6 KB (865 words) - 12:16, 17 November 2017
- ...detectors) to reduce the power consumption but also use energy harvesting system such as microbial fuel cell. The communication plays also an important role ...ment of novel zero-power sensors that act as a trigger for the rest of the system when important event is detected and consume zero-power between two detecti5 KB (745 words) - 17:21, 31 January 2018
- [[Category:System Design]]3 KB (409 words) - 13:58, 9 November 2017
- [[Category:System Design]] [[Category:System on Chips for IoTs]]4 KB (460 words) - 21:42, 30 January 2018
- ...iver, digital baseband processing, and an application processor. Such a RF System-on-Chip (RF-SoC) is mandatory to achieve minimal manufacturing costs.3 KB (344 words) - 01:45, 10 February 2021
- ...nology to cellular connectivity by covering dead spots or as a stand-alone system. NB-IoT itself is seen as a possible technology for satellite IoT (sIoT) an ...upport satellite communication channels. A thorough simulative analysis of system performance will enable the identification of critical bottlenecks. These s3 KB (393 words) - 13:53, 13 November 2020
- [[Category:System Design]] [[Category:System Design]]3 KB (317 words) - 14:40, 14 April 2021
- ...bedded image processing. The ambitious goal is to build a self-sustainable system that allows simple image processing to be implemented on-board the device. ...dy the required components for building a miniature ultra-low power camera system and develop a demonstration platform based on our ULP image sensor chip (de4 KB (602 words) - 10:45, 31 January 2023
- both dramatically simplifying the programmability of such a heterogeneous system. ...al of this project is to implement TLB invalidations for our heterogeneous system.6 KB (796 words) - 17:19, 18 November 2019
- ...is a great cellular IoT research opportunity and gives deep insights into system engineering.2 KB (269 words) - 13:15, 31 October 2019
- ...in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost as well as power consumption show ro1 KB (217 words) - 11:01, 18 March 2019
- ...detection and location of such seizures. When aiming a low power implanted system the large amount of data has to be efficiently reduced. iEEG signals are sp5 KB (641 words) - 13:36, 9 September 2020
- ...exploit their theoretical potential is challenging due to the high overall system complexity. ...our chance to explore and work on (almost) any layer of a running computer system and contribute to energy-efficient next-generation computing platforms!3 KB (421 words) - 18:41, 28 October 2020
- ...be deployed on COTS hardware that limit the memory interference within the system, such that real-time guarantees can be provided, enabling the use of these2 KB (286 words) - 18:48, 10 November 2020
- ...ize, and will thus constitute an increasingly larger fraction of the total system power consumption. * '''2020''' - V. Niculescu et Al., "An Energy-efficient Localization System for Imprecisely Positioned Sensor Nodes with Flying UAVs", ''2020 IEEE 18th14 KB (2,077 words) - 15:02, 13 June 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (621 words) - 18:09, 9 October 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (549 words) - 12:35, 28 November 2022
- At IIS, we are exploring the next generation of medical ultrasound system. Our Flagship projects are: ...rable solutions as well as alternatives to the traditional bulky and rigid system designs.6 KB (797 words) - 16:16, 23 February 2024
- ...://iis-projects.ee.ethz.ch/index.php/Biomedical_System_on_Chips Biomedical System on Chips] as well as [http://iis-projects.ee.ethz.ch/index.php/Deep_Learnin10 KB (1,341 words) - 10:46, 25 April 2018
- * Motivation to build and test a real system and acquiring field data [[Category:System Design]]7 KB (1,003 words) - 17:30, 6 December 2021
- [[Category:System Design]] [[Category:System Design]]3 KB (354 words) - 16:06, 6 May 2019
- ...t the FPGA hardware using Verilog or VHDL. You will use Xilinx ISE, Xilinx System Generator, Chipscope, Modelsim, Matlab and Mathamatica as development tools [[Category:System Design]]5 KB (599 words) - 09:03, 21 December 2017
- [[Category:System Design]] [[Category:System Design]]3 KB (329 words) - 11:43, 20 August 2021
- ...classification accuracy and energy efficiency and to further optimize the system. [[Category:System Design]]5 KB (697 words) - 13:36, 11 January 2018
- 3D sonar sensors. The proposed system architecture will be developed around an Ultra low power parallel processor * Design of the full system to achieve an autonomous sensor. (PCB design, Low power Techniques, etc.)4 KB (518 words) - 11:40, 2 February 2018
- ...he student he can be involved on the design of the IC, the layout, or at a system and application levler. The wake-up receiver should achieves power consumpt ...classification accuracy and energy efficiency and to further optimize the system.5 KB (686 words) - 11:54, 2 February 2018
- ...on the human body. The student will work to design a whole application and system exploiting the zero-power communication receiver/sensor. ...classification accuracy and energy efficiency and to further optimize the system.4 KB (585 words) - 11:58, 2 February 2018
- * Familiarity with embedded system programming in C.5 KB (623 words) - 16:14, 20 February 2018
- * Familiarity with embedded system programming in C.7 KB (1,008 words) - 16:20, 20 February 2018
- ...tions, the student will apply the identified modifications to the existing system and develop the additional software tasks. Lastly, an evaluation of the pro * Familiarity with embedded system programming in C.6 KB (842 words) - 16:18, 20 February 2018
- The largest part of any aerial vehicle’s power budget is the mechanical system. A blimp, however, requires significantly less power for horizontal propuls * Familiarity with embedded system programming in C.6 KB (914 words) - 16:17, 20 February 2018
- ...nce of several underlying life-long processes, e.g., respiration, vascular system dynamic, muscle contraction. ...ngs vision, the point-of-contact electronic that interfaces the biological system with the cloud-based digital world is very critical due to unique specifica2 KB (327 words) - 19:55, 22 February 2018
- [[Category:Biomedical System on Chips]] ...ld you choose to accept it, is to join our active research into biomedical system design. The approach is to used state-of-the-art machine learning algorithm4 KB (597 words) - 19:15, 9 March 2020
- ...novel solutions to reducing the energy consumption of such devices on the system-level are required. One of the key ideas in event-driven computing is the r * Basic knowledge of the C language and embedded system programming3 KB (433 words) - 15:16, 4 August 2022
- ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory5 KB (706 words) - 17:41, 19 June 2019
- ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the The goal of this project is to design and integrate a full system configuration of CPU and GPU applications that can be executed concurrently4 KB (499 words) - 17:40, 19 June 2019
- #REDIRECT [[BLISS - Battery-Less Identification System for Security]]69 bytes (8 words) - 14:54, 25 April 2018
- [[Category:Biomedical System on Chips]]3 KB (358 words) - 15:59, 18 February 2019
- ...rs that implements the RISC-V ISA. It has been designed for small embedded system platforms mostly used in IoT devices. Its ISA implements RISC-V's RV32IMFC ...build a testbench for the core to test the IP isolated by the rest of the system. (~3-4 weeks)4 KB (661 words) - 08:38, 20 January 2021
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]3 KB (381 words) - 14:17, 28 January 2023
- ====[[Biomedical System on Chips|Biomedical System on Chips]]==== ===[[Biomedical System on Chips|Biomedical System on Chips]]===2 KB (311 words) - 12:02, 5 December 2018
- ...studies in (primary+) schools we're developing an interesting edutainment system for kids together with the PR of D-ITET and [http://www.wysszurich.uzh.ch w The idea is to create a playful, central interaction system accompanied by distributable modules for the kids to solve and play with.3 KB (447 words) - 16:11, 18 September 2018
- ...c capacitance, a minimum amount of energy needs to be harvested before the system can do useful work. A specially designed cold-start circuit can significant ...ll investigate and design a new cold-start circuit that aims to reduce the system’s start-up time. Depending on the chosen architecture, the choice of MPPT5 KB (638 words) - 15:41, 10 November 2020
- ...s thesis it will be possible to learn the whole the design cycle including system simulation and layout as a master student, for a semester thesis the work i : 20% System Investigations (Calculation, Matlab)2 KB (359 words) - 16:06, 6 May 2019
- ...f needed dedicated hardware blocks can be deisgned and integrated into the system. If time allows the performance of the implementation will be verified with [[Category:System Design]]4 KB (566 words) - 15:50, 9 February 2021
- : 40% System Simulation (Matlab/Simulink)2 KB (356 words) - 15:55, 6 May 2019
- ...hanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level d ...dictates battery size, the most critical factor in any volume-constrained system.4 KB (597 words) - 16:57, 12 July 2022
- ...e thesis it will be possible to learn the whole the design cycle including system simulation and layout as a master student, for a semester thesis the work i2 KB (347 words) - 11:43, 20 August 2021
- ...and not in the chips that we designed ourselves, rendering many low-level system management jobs challenging and cumbersome. In this project, you will exten *Some experience with hardware design (VHDL/(System-)Verilog), for example completion of VLSI I lecture2 KB (240 words) - 16:57, 12 July 2022
- * Identify critical network performance parameters to be integrated in the system design * Implement a BLE mesh reference system by compiling Nordic’s SIGMesh stack onto the Thingy52 IoT dev kits (or si5 KB (685 words) - 15:34, 10 November 2020
- ...iomedical acquisition and processing platform is standalone operation: The system must be able to provide all required supply voltages and clock frequencies [[Category:Biomedical System on Chips]]2 KB (268 words) - 16:57, 12 July 2022
- [[Category:System Design]]5 KB (622 words) - 15:36, 10 November 2020
- ...classification accuracy, and energy efficiency and to further optimize the system. [[Category:System Design]]5 KB (631 words) - 15:36, 10 November 2020
- ...ring this project you will map a 32bit PULPino/PULPissimo micro-controller system to the Altera DE-10 Lite board, adapt the design flow so that prospective u [[Category:System Design]]4 KB (497 words) - 16:50, 21 June 2018
- ...ing” portion of the signal. This reduce the bandwidth from the recording system depending on the signal activity (more interesting events --> higher bandwi In the context of action potentials, a neural recording system can send to a digital processor only the spikes and do not send anything wh8 KB (1,269 words) - 18:40, 5 September 2019
- ...a solution to be used in our high-performance GPU-based ultrasound imaging system. * Implementation of the RDMA subsystem for our ultrasound system2 KB (340 words) - 16:58, 16 September 2022
- ...with the functions provided by the body itself. Human Intranet presents a system vision in which, for example, disease would be treated by chronically measu * '''System-level design and testing''' (Altium, C-programming)17 KB (2,419 words) - 20:09, 10 March 2024
- ...rrival (OTDOA) such as covered in [[Implementation of a NB-IoT Positioning System]] or [[OTDOA Positioning for LTE Cat-M]]1 KB (204 words) - 13:14, 31 October 2019
- ...r rhythms (SMR) and movement-related cortical potentials (MRCP). SMR-based system make use of event-related synchronisation/desynchronisation (ERD/ERS) behav4 KB (594 words) - 09:18, 16 September 2021
- ..., non-invasive method to measure kidney performance via an external sensor system to avoid the use of urinary catheters for this subgroup of patients, thereb ...classification accuracy, and energy efficiency and to further optimize the system. The work includes the modeling and design of a suited impedance sensor, it6 KB (857 words) - 15:37, 10 November 2020
- ...ional demands on hospital staff. The goal of the project is set-up a whole system that includes readers and mobile tags. For example in the case of the RFID, [[Category:System Design]]6 KB (780 words) - 15:37, 10 November 2020
- ...imaging only and has only been demonstrated with large research ultrasound system. ...t Microbubbles (this may requires to modify the imaging method used by the system)3 KB (391 words) - 20:49, 12 November 2020
- ...al ultrasound probe to capture the raw sensor data and transfer it to a PC system for fully software-defined processing, offering unprecedented flexibility a ...we at IIS have demonstrated that this novel architecture is feasible for a system with 64 channels ([[LightProbe]]), it yet has to be demonstrated that this2 KB (250 words) - 20:48, 12 November 2020
- ...esinged node will also include energy harvesting to allow a self-sustainig system. [[Category:System Design]]5 KB (744 words) - 15:37, 10 November 2020
- [[Category:System Design]]4 KB (594 words) - 15:38, 10 November 2020
- '''Embedded stereo visual inertial system''' ...omputing system. In addition, some image processing should be done at this system to reduce the overhead of the network and to compute the first steps on the6 KB (895 words) - 16:27, 30 October 2020
- ...eting two application scenarios: behind-the-ear EEG and ECG wristband. The system will also be used to explore applications scenarios for augmenting current [[Category:System Design]]6 KB (761 words) - 15:38, 10 November 2020
- ...l set of basic operations on high-dimensional vectors, we obtain hybrid AI system (HAS) that makes it possible to represent and manipulate data in ways famil *General interest in Deep Learning and memory/system design9 KB (1,330 words) - 15:20, 15 March 2024