Analog
From iis-projects
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Projects that are part of the analog and mixed signal design group.
Available Projects
- Digital Control of a DC/DC Buck Converter
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- Analog building blocks for mmWave manipulation
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- Bluetooth Low Energy network with optimized data throughput
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- 5G Cellular RF Front-end Design in 22nm CMOS Technology
- Design of Charge-Pump PLL in 22nm for 5G communication applications
Digital design projects in the area of telecommunications are also available.
Active Projects
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
Completed Projects
2018
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- Interference Cancellation for EC-GSM-IoT
2017
- Turbo Equalization for Cellular IoT
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
2016
- Switched Capacitor Based Bandgap-Reference
- High performance continous-time Delta-Sigma ADC for biomedical applications
- GUI-developement for an action-cam-based eye tracking device
- Efficient NB-IoT Uplink Design
- Internet of Things Network Synchronizer
- System Analysis and VLSI Design of NB-IoT Baseband Processing
2015
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Baseband Meets CPU
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Time and Frequency Synchronization in LTE Cat-0 Devices
2014
2013
- Wireless Biomedical Signal Acquisition Device
- Flexible Front-End Circuit for Biomedical Data Acquisition
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
2012
- Data Mapping for Unreliable Memories
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- High Throughput Turbo Decoder Design
- Turbo Decoder Design for High Code Rates
- Channel Decoding for TD-HSPA
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- Successive Interference Cancellation for 3G Downlink
- Channel Estimation for TD-HSPA
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- MatPHY: An Open-Source Physical Layer Development Framework
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- High Performance Cellular Receivers in Very Advanced CMOS
- Multi-Band Receiver Design for LTE Mobile Communication
- High-Resolution, Calibrated Folding ADCs
