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Showing below up to 50 results in range #331 to #380.
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- Event-Driven Vision on an embedded platform
- Event-based navigation on autonomous nano-drones
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the HERO SDK to support asynchronous offloading (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- Eye movements
- Eye tracking
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
- FFT-based Convolutional Network Accelerator
- FFT HDL Code Generator for Multi-Antenna mmWave Communication
- FPGA
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
- FPGA mapping of RPC DRAM
- Fabian Schuiki
- Fast Accelerator Context Switch for PULP
- Fast Simulation of Manycore Systems (1S)
- Fast Wakeup From Deep Sleep State
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fault-Tolerant Floating-Point Units (M)
- Fault Tolerance
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Federico Villani
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Final Presentation
- Final Report
