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Showing below up to 50 results in range #481 to #530.
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- Multiuser Equalization and Detection for 3GPP TD-SCDMA (6 revisions)
- Towards Self Sustainable UAVs (6 revisions)
- Compression of iEEG Data (6 revisions)
- Learning Image Decompression with Convolutional Networks (6 revisions)
- Novel Methods for Jammer Mitigation (6 revisions)
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets (6 revisions)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (6 revisions)
- Efficient Synchronization of Manycore Systems (M/1S) (6 revisions)
- Writing a Hero runtime for EPAC (1-3S/B) (6 revisions)
- Moritz Schneider (6 revisions)
- Ultra-Efficient Visual Classification on Movidius Myriad2 (6 revisions)
- Implementing DSP Instructions in Banshee (1S) (6 revisions)
- Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing (6 revisions)
- Next Generation Channel Decoder (6 revisions)
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors (6 revisions)
- Floating-Point Divide & Square Root Unit for Transprecision (6 revisions)
- Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening (6 revisions)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (6 revisions)
- Exploring Algorithms for Early Seizure Detection (6 revisions)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (6 revisions)
- MemPool on HERO (1S) (6 revisions)
- New RVV 1.0 Vector Instructions for Ara (6 revisions)
- Novel Metastability Mitigation Technique (6 revisions)
- Self Aware Epilepsy Monitoring (6 revisions)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (6 revisions)
- FPGA Optimizations of Dense Binary Hyperdimensional Computing (6 revisions)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (6 revisions)
- Implementing Configurable Dual-Core Redundancy (6 revisions)
- LightProbe - Ultracompact Power Supply PCB (6 revisions)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) (6 revisions)
- IBM Research–Zurich (6 revisions)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (6 revisions)
- VLSI Design of an Asynchronous LDPC Decoder (6 revisions)
- Switched Capacitor Based Bandgap-Reference (6 revisions)
- Channel Estimation for 3GPP TD-SCDMA (6 revisions)
- System Emulation for AR and VR devices (6 revisions)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (6 revisions)
- Enabling Efficient Systolic Execution on MemPool (M) (6 revisions)
- Change-based Evaluation of Convolutional Neural Networks (6 revisions)
- FPGA mapping of RPC DRAM (6 revisions)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (6 revisions)
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA (6 revisions)
- CMOS power amplifier for field measurements in MRI systems (6 revisions)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (6 revisions)
- Beat Cadence (6 revisions)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (6 revisions)
- Autonomous Smart Watches: Hardware and Software Desing (6 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Putting Together What Fits Together - GrÆStl (7 revisions)
