Pages with the most categories

Showing below up to 50 results in range #71 to #120.

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71. EEG earbud‏‎ (11 categories)
72. Mixed-Precision Neural Networks for Brain-Computer Interface Applications‏‎ (11 categories)
73. Evaluating SoA Post-Training Quantization Algorithms‏‎ (11 categories)
74. Resource Partitioning of Caches‏‎ (11 categories)
75. LLVM and DaCe for Snitch (1-2S)‏‎ (11 categories)
76. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (11 categories)
77. Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers‏‎ (11 categories)
78. Waterflow Monitoring with Doppler Ultrasound (1S)‏‎ (11 categories)
79. Fault-Tolerant Floating-Point Units (M)‏‎ (11 categories)
80. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (11 categories)
81. In-ear EEG signal acquisition‏‎ (11 categories)
82. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)‏‎ (11 categories)
83. Modeling FlooNoC in GVSoC (S/M)‏‎ (11 categories)
84. Non-blocking Algorithms in Real-Time Operating Systems‏‎ (11 categories)
85. Spectrometry for Environmental Monitoring (1-2S/M)‏‎ (11 categories)
86. Structural Health Monitoring (SHM) System (1-2S/M)‏‎ (11 categories)
87. A Flexible Peripheral System for High-Performance Systems on Chip (M)‏‎ (11 categories)
88. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)‏‎ (11 categories)
89. Predict eye movement through brain activity‏‎ (11 categories)
90. Routing 1000s of wires in Network-on-Chips (1-2S/M)‏‎ (11 categories)
91. Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications‏‎ (10 categories)
92. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (10 categories)
93. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (10 categories)
94. Zephyr RTOS on PULP‏‎ (10 categories)
95. Floating-Point Divide & Square Root Unit for Transprecision‏‎ (10 categories)
96. IoT Turbo Decoder‏‎ (10 categories)
97. A Unified Compute Kernel Library for Snitch (1-2S)‏‎ (10 categories)
98. Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex‏‎ (10 categories)
99. Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)‏‎ (10 categories)
100. Deep Learning-based Global Local Planner for Autonomous Nano-drones‏‎ (10 categories)
101. Machine Learning for extracting Muscle features from Ultrasound raw data‏‎ (10 categories)
102. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs‏‎ (10 categories)
103. Enhancing our DMA Engine with Fault Tolerance‏‎ (10 categories)
104. PULP Freertos with LLVM‏‎ (10 categories)
105. An FPGA-Based Testbed for 3G Mobile Communications Receivers‏‎ (10 categories)
106. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)‏‎ (10 categories)
107. Timing Channel Mitigations for RISC-V Cores‏‎ (10 categories)
108. Machine Learning for extracting Muscle features using Ultrasound‏‎ (10 categories)
109. Extend the RI5CY core with priviledge extensions‏‎ (10 categories)
110. Ibex: Tightly-Coupled Accelerators and ISA Extensions‏‎ (10 categories)
111. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)‏‎ (10 categories)
112. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)‏‎ (10 categories)
113. Big Data Analytics Benchmarks for Ara‏‎ (10 categories)
114. Low Latency Brain-Machine Interfaces‏‎ (10 categories)
115. Graph neural networks for epileptic seizure detection‏‎ (10 categories)
116. PULPonFPGA: Hardware L2 Cache‏‎ (10 categories)
117. Softmax for Transformers (M/1-2S)‏‎ (10 categories)
118. Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)‏‎ (10 categories)
119. Taping a Safer Silicon Implementation of Snitch (M/2-3S)‏‎ (10 categories)
120. On-Board Software for PULP on a Satellite‏‎ (10 categories)

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