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Showing below up to 50 results in range #801 to #850.
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- Successive Approximation Register (SAR) ADC
- Successive Interference Cancellation for 3G Downlink
- Super Resolution Radar/Imaging at mm-Wave frequencies
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Switched Capacitor Based Bandgap-Reference
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- System Emulation for AR and VR devices
- TCNs vs. LSTMs for Embedded Platforms
- Taimir Aguacil
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Tbenz
- Telecommunications
- Template
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Test page
- Test project
- Testbed Design for Self-sustainable IoT Sensors
- Theory, Algorithms, and Hardware for Beyond 5G
- Thermal Control of Mobile Devices
- Through Wall Radar Imaging using Machine Learning
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Timing Channel Mitigations for RISC-V Cores
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Toward Superposition of Brain-Computer Interface Models
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Towards Autonomous Navigation for Nano-Blimps
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards Online Training of CNNs: Hebbian-Based Deep Learning
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards Self Sustainable UAVs
- Towards The Integration of E-skin into Prosthetic Devices
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards global Brain-Computer Interfaces
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Decoder Design for High Code Rates
- Turbo Equalization for Cellular IoT
- Ultra-Efficient Visual Classification on Movidius Myriad2
