Pages with the fewest revisions
From iis-projects
Showing below up to 50 results in range #501 to #550.
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- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Ultrasound Low power WiFi with IMX7 (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Development of a Rockfall Sensor Node (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- Efficient Search Design for Hyperdimensional Computing (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Transforming MemPool into a CGRA (M) (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (7 revisions)
- Zephyr RTOS on PULP (7 revisions)
- EEG artifact detection for epilepsy monitoring (7 revisions)
- Fault Tolerance (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- Characterization techniques for silicon photonics-Lumiphase (7 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Weekly Reports (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- NVDLA meets PULP (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- Sandro Belfanti (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
