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From iis-projects
Showing below up to 100 results in range #201 to #300.
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- GSM Voice Capacity Evolution - VAMOS (10 revisions)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (10 revisions)
- Quest for the smallest Turing-complete core (2-3G) (10 revisions - redirect page)
- Cell-Free mmWave Massive MIMO Communication (10 revisions)
- A Wireless Sensor Network for HPC monitoring (10 revisions)
- BigPULP: Shared Virtual Memory Multicluster Extensions (10 revisions)
- Design of a VLIW processor architecture based on RISC-V (10 revisions)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (10 revisions)
- Cell Measurements for the 5G Internet of Things (10 revisions)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces (10 revisions)
- Event-Driven Vision on an embedded platform (10 revisions)
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B) (10 revisions)
- Design of Charge-Pump PLL in 22nm for 5G communication applications (10 revisions)
- Time Gain Compensation for Ultrasound Imaging (10 revisions)
- Gomeza old project3 (10 revisions)
- Wearable Ultrasound for Artery monitoring (10 revisions)
- Self-Supervised User Positioning in Cell-Free Massive MIMO Systems (10 revisions)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (10 revisions)
- Implementation of an Accelerator for Retentive Networks (1-2S) (10 revisions)
- All the flavours of FFT on MemPool (1-2S/B) (10 revisions)
- Matteo Perotti (10 revisions)
- Next Generation Synchronization Signals (9 revisions)
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration (9 revisions)
- Machine Learning for extracting Muscle features using Ultrasound 2 (9 revisions)
- Karim Badawi (9 revisions)
- Feature Extraction for Speech Recognition (1S) (9 revisions)
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces (9 revisions)
- Design and Implementation of an Approximate Floating Point Unit (9 revisions)
- Knowledge Distillation for Embedded Machine Learning (9 revisions)
- Hyper-Dimensional Computing Based Predictive Maintenance (9 revisions)
- Efficient Implementation of an Active-Set QP Solver for FPGAs (9 revisions)
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning (9 revisions)
- HERO: TLB Invalidation (9 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (9 revisions)
- Hyper Meccano: Acceleration of Hyperdimensional Computing (9 revisions)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication (9 revisions)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (9 revisions)
- Real-Time Pedestrian Detection For Privacy Enhancement (9 revisions)
- Runtime partitioning of L1 memory in Mempool (M) (9 revisions)
- Integrating Hardware Accelerators into Snitch (9 revisions)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (9 revisions)
- Harald Kröll (9 revisions)
- Improved Reacquisition for the 5G Cellular IoT (9 revisions)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (9 revisions)
- Automatic unplugging detection for Ultrasound probes (9 revisions)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (9 revisions)
- Ultrasound-EMG combined hand gesture recognition (9 revisions)
- DC-DC Buck converter in 65nm CMOS (9 revisions)
- Practical Reconfigurable Intelligent Surfaces (RIS) (9 revisions)
- Energy Efficient SoCs (9 revisions)
- Configurable Ultra Low Power LDO (9 revisions)
- Gomeza old project2 (9 revisions)
- Real-time View Synthesis using Image Domain Warping (9 revisions)
- Michael Rogenmoser (9 revisions)
- A Multiview Synthesis Core in 65 nm CMOS (9 revisions)
- OpenRISC SoC for Sensor Applications (9 revisions)
- Improved State Estimation on PULP-based Nano-UAVs (9 revisions)
- Freedom from Interference in Heterogeneous COTS SoCs (9 revisions)
- Real-time eye movement analysis on a tablet computer (9 revisions)
- Minimal Cost RISC-V core (9 revisions)
- Hardware Accelerated Derivative Pricing (9 revisions)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (9 revisions)
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication (9 revisions)
- Gomeza old project4 (9 revisions)
- Time and Frequency Synchronization in LTE Cat-0 Devices (9 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- NVDLA meets PULP (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- Sandro Belfanti (8 revisions)
- Low-Power Environmental Sensing (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- Weekly Reports (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- Pirmin Vogel (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Multi issue OoO Ariane Backend (M) (8 revisions)
- PREM Runtime Scheduling Policies (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
- BCI-controlled Drone (8 revisions)
- Fast Wakeup From Deep Sleep State (8 revisions)
