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• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  In this project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient cont : 40% Architecture Design
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  # Specification, RTL design and host software development of a trace debugger for one of our custom RIS # FPGA evaluation of your implementation.
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  ...arch operations in HD computing. You would develop RTL implementation with FPGA prototyping. : Architecture Design
  3 KB (366 words) - 15:39, 10 November 2020
• Creating a HDMI Video Interface for PULP
  ...ted native differential signalling this is easier to implement in a purely digital fashion. ...ip (or external) frame-buffer. At first your implementation will target an FPGA (Xilinz Zynq) implementation as a first prototype but upon successful compl
  4 KB (603 words) - 09:37, 10 July 2018
• BigPULP: Multicluster Synchronization Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (VHDL, FPGA/ASIC Design, C)
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (C, VHDL, FPGA/ASIC Design)
  6 KB (801 words) - 15:05, 23 August 2018
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  * '''[[Design Review]]''' [[Category:Digital]]
  3 KB (409 words) - 13:58, 9 November 2017
• IoT Turbo Decoder
  [[File:High Throughput Turbo Decoder Design.png|400px|thumb|A previous, high throughput, Turbo Decoder developed at IIS ...processor cluster. The final design can either be mapped to an FPGA, or an ASIC.
  3 KB (427 words) - 09:37, 14 September 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...phys.ethz.ch/ Physics Department of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real world, t ...puts that connect to the AC701’s FMC connector and get familiar with the design of the unit and it’s purpose.
  4 KB (460 words) - 21:42, 30 January 2018
• Wireless Communication Systems for the IoT
  ...ns, which incorporate analog sensor / actuator front ends, RF-transceiver, digital baseband processing, and an application processor. Such a RF System-on-Chip ...an RF SoC design is the hardware- and energy-efficient realization of the digital baseband algorithms in which we constantly offer various semester and maste
  3 KB (344 words) - 01:45, 10 February 2021
• HERO: TLB Invalidation
  ...evaluation platform combines a modern ARMv8 multicluster CPU with a Xilinx FPGA capable of implementing PULP with up to 8 clusters and a total of 64 cores. : 50% Design and Implementation (SystemVerilog, C, FPGA/ASIC Design)
  6 KB (796 words) - 17:19, 18 November 2019
• Beat Cadence
  ...g a highly integrated SoC for the IoT in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost ...s project is a perfect opportunity to get to know state-of-the-art HLS and digital architecture approaches and to show that a human is still better than a mac
  1 KB (217 words) - 11:01, 18 March 2019
• Aliasing-Free Wavetable Music Synthesizer
  [[File:Iip_syneth.png|300px|thumb|SYNƎTH wavetable synthesizer ASIC project. ]] ...integrated circuits (ASICs). Furthermore, it is practically challenging to design wavetable oscillators that do not produce aliasing artifacts, especially if
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  ...a large number of freely programmable operators resulting in endless sound-design possibilities compared to existing FM synthesizers. ...he architecture in a modern CMOS process and send the modular FM synthesis ASIC to fabrication.
  5 KB (549 words) - 12:35, 28 November 2022
• Hyperdimensional Computing
  * '''Algorithmic''' design and optimizations (Matlab/ Python) * '''Hardware and digital architecture''' design
  10 KB (1,341 words) - 10:46, 25 April 2018
• CMOS power amplifier for field measurements in MRI systems
  .... The thesis offers the possibility to study main aspects of analog and RF design, such as noise, linearity, matching, small signal-concepts and power consum : 50% Design
  3 KB (354 words) - 16:06, 6 May 2019
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...ecord and display the signal processing results. The interface between the FPGA and ADC board, DDR3 and PC is already implemented. ...with signal processing in the context of quantum computing experiments and FPGA hardware implementations
  5 KB (599 words) - 09:03, 21 December 2017
• Inductive Charging Circuit for Implantable Devices
  : 30% Design * '''[[Design Review]]'''
  3 KB (329 words) - 11:43, 20 August 2021
• Extend the RI5CY core with priviledge extensions
  ...plus custom instructions that have been designed to efficiently deal with digital-signal-processing applications typical for near-sensor systems. ...lace. The student will focus especially on the memory exeptions and in the design of an MMU. The student is required to extend the testbench to emulated the
  4 KB (661 words) - 08:38, 20 January 2021
• Wearables for Sports and Life Enhancement
  : 40% ASIC Design * '''[[Design Review]]'''
  3 KB (381 words) - 14:17, 28 January 2023
• Physics is looking for PULP
  ...LPissimo micro-controller system to the Altera DE-10 Lite board, adapt the design flow so that prospective users can develop their programs, and transfer the : 50% FPGA Design Mapping
  4 KB (497 words) - 16:50, 21 June 2018
• Human Intranet
  <!--For example, to design the ''brain'' of our physical computing (i.e., the compute/interpret compon * '''Algorithm design and optimizations''' (Python)
  17 KB (2,419 words) - 20:09, 10 March 2024
• Elliptic Curve Accelerator for zkSNARKs
  ...will devise an optimal architecture for the problem and implement it on an FPGA. : 40% Digital Design
  5 KB (614 words) - 15:02, 4 March 2019
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  : Embedded systems and PCB design : 35% Embedded System Design
  6 KB (820 words) - 12:13, 23 July 2023
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  : Analog Mixed Signal Design : PCB Design
  5 KB (644 words) - 18:18, 21 July 2023
• NAND Flash Open Research Platform
  : 40% PCB Design ...ct would involve designing a PCB daughterboard that can be connected to an FPGA or microcontroller.
  4 KB (551 words) - 11:06, 11 July 2019
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  ...s simulation scheme, various DHBT systems could be simulated and potential design ameliorations could be proposed. : 40% ASIC Design
  4 KB (517 words) - 17:09, 16 September 2021
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  ...ded with custom instructions to target high energy efficiency when running digital signal processing functions. It can be attached to the Ariane subsystem vi ...whole system to the FPGA. Note that Ariane has already been mapped to the FPGA and it is able to boot Linux, the student can start for the already done wo
  7 KB (1,030 words) - 19:05, 29 January 2021
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
  ...ly quantized CNNs (''YodaNN'' [Andri2017]), in the Ergo project we want to design a PULP-based entire computation cluster around a set of deep, fast and low- ...r/area characteristics) intrinsically attractive. In this thesis, you will design a novel heterogeneous interconnect for the PULP system to connect high-thro
  7 KB (961 words) - 21:21, 29 January 2019
• Timing Channel Mitigations for RISC-V Cores
  ...are among the remaining unsolved problems in secure hardware architecture design, and it is argued that '''security needs a new hardware-software contract'' ...is process shall be fed back to the RISC-V community in order to guide the design of future secure RISC-V systems.
  6 KB (915 words) - 18:16, 20 May 2020
• Developing a small portable neutron detector for detecting smuggled nuclear material
  ...st and digital solution is likely to be most suitable, which is why use of FPGA is planned. This preferably has an appropriate user interface, battery powe ...the needs of the target application in a mobile device (very likely to be FPGA-based solution, although alternative will be considered)
  5 KB (623 words) - 10:32, 5 November 2019
• ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
  * '''[[Design Review]]''' [[Category:Digital]]
  6 KB (735 words) - 12:12, 23 July 2023
• Floating-Point Divide & Square Root Unit for Transprecision
  ...ng one into a transprecision-capable unit. Furthermore, you will take your design through most of the steps necessary for manufacturing it on an actual IC to ...research to help developing a transprecision-enabled platform for ASIC and FPGA targets. You will learn:
  8 KB (1,135 words) - 17:09, 29 July 2020
• Channel Estimation for 5G Cellular IoT and Fast Fading Channels
  ...it as a standalone ASIC, or integrate it into our RF SoC and test it on an FPGA. : 40% Hardware Design (HLS/VHDL)
  3 KB (415 words) - 18:54, 29 October 2020
• FPGA Testbed Implementation for Bluetooth Indoor Positioning
  .... As a first step towards a Bluetooth LE modem with positioning support, a digital baseband receiver capable of detecting Bluetooth LE packets and estimating ...seband block. Then you will develop the required software to interface the digital baseband block and if needed extend the hardware to provide additional func
  3 KB (431 words) - 21:47, 18 November 2019
• Heroino: Design of the next CORE-V Microcontroller
  *Use fusesoc to generate RTL lists, generate top-level and FPGA synthesis. Flattened dependencies can have out-of-tree source file listings *FPGA bring-up, debug connection, preloading of memories (DRAM).
  9 KB (1,314 words) - 00:01, 7 February 2021
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
  Design for Reliability (DfR) is a must for such critical domains. Traditional faul 2. Specification and RTL design on top of an OpenPULP cluster with Ibex processor cores (~2 person months).
  6 KB (980 words) - 14:46, 2 June 2021
• Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
  * '''[[Design Review]]''' [[Category:Digital]]
  5 KB (584 words) - 12:09, 29 October 2020
• Semi-Custom Digital VLSI for Processing-in-Memory
  ...conductor devices. As such, these architectures are often (i) difficult to design, test, or migrate to other technology nodes, due to their analog component, ...e, that it can achieve better area- and energy-efficiency than traditional digital architectures that perform the same operation. These results demonstrate th
  7 KB (882 words) - 14:33, 28 July 2021
• Ibex: FPGA Optimizations
  ...ant to the RISC-V specification, cleaning up the codebase, documenting the design, adding new features such as support for U-Mode and PMP, considerable effor ...y cores of comparable performance such as [https://www.xilinx.com/products/design-tools/microblaze.html Xilinx MicroBlaze].
  5 KB (666 words) - 09:45, 28 August 2020
• Accurate deep learning inference using computational memory
  : Basics of Digital and Analog Design (VLSI1/AIC) * '''[[Design Review]]'''
  5 KB (628 words) - 12:51, 17 April 2020
• ASIC Implementation of Jammer Mitigation
  ...te user equipments. The signal processing for this takes place in a custom ASIC.]] ...as an efficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology.
  5 KB (662 words) - 13:31, 10 May 2023
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  ...ator that solely relies on standard cells as state holding elements of the design. ...r that hopefully match the characteristics of the memories used in the old design. SCMs provide arbitrary amounts of read and write bandwidth which is a comm
  7 KB (1,032 words) - 15:31, 16 November 2020
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
  ...and II or equivalent: Understanding of at least one RTL language and ASIC design principles. [[Category:Digital]]
  11 KB (1,675 words) - 15:40, 15 March 2021
• Peak-to-average power Reduction
  : 50% VLSI Design * '''[[Design Review]]'''
  4 KB (513 words) - 14:16, 24 November 2021
• VLSI Implementation of a 5G Ciphering Accelerator
  ...and-route tool flow. The work concludes with a comparison of the generated ASIC with state of the art. : 40% Architectural Design
  3 KB (404 words) - 10:05, 9 February 2021
• Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
  * '''[[Design Review]]''' [[Category:Digital]]
  8 KB (931 words) - 17:27, 23 November 2021
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  * Type: ASIC Semester Thesis [[Category:Digital]]
  8 KB (1,214 words) - 15:18, 9 July 2021
• Cell-Free mmWave Massive MIMO Communication
  * '''[[Design Review]]''' [[Category:Digital]]
  7 KB (882 words) - 21:34, 13 July 2022
• Practical Reconfigurable Intelligent Surfaces (RIS)
  ...the improvement provided by these devices in terms of energy efficiency. A design focused on this purpose is developed not only for the transmit power alloca * '''[[Design Review]]'''
  8 KB (1,011 words) - 12:25, 16 November 2023

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