Difference between revisions of "High Performance SoCs"

Latest revision as of 16:21, 11 November 2020

High-Performance Systems-on-Chip

The Snitch cluster couples tiny RISC-V Snitch cores with performant double-precision FPUs to minimize the control-to-compute ratio; it uses hardware loop buffers and stream semantic registers to achieve almost full FPU utilization.

Baikonur, a 22 nm chip integrating two application-grade RISC-V Ariane cores and 3 Snitch clusters with 8 cores each.

Concept art for Manticore, a Snitch-based 22 nm system with 4096 cores on multiple chiplets and with HBM2 memory.

Today, a multitude of data-driven applications such as machine learning, scientific computing, and big data demand an ever-increasing amount of parallel floating-point performance from computing systems. Increasingly, such applications must scale across a wide range of applications and energy budgets, from supercomputers simulating next week's weather to your smartphone cameras correcting for low light conditions.

This brings challenges on multiple fronts:

• Energy Efficiency becomes a major concern: As logic density increases, supplying these systems with energy and managing their heat dissipation requires increasingly complex solutions.

• Memory bandwidth and latency become a major bottleneck as the amount of processed data increases. Despite continuous advances, memory lags behind computing in scaling, and many data-driven problems today are memory-bound.

• Parallelization and scaling bring challenges of their own: on-chip interconnects may introduce significant area and performance overheads as they grow, and both the data and instruction streams of cores may compete for valuable memory bandwidth and interfere in a destructive way.

While all state-of-the-art high-performance computing systems are constrained by the above issues, they are also subject to a fundamental trade-off between efficiency and flexibility. This forms a design space which includes the following paradigms:

• Accelerators are designed to do one thing very well: they are very energy efficient and performant and usually offer predetermined data movement. However, they are not or barely programmable, inflexible, and monolithic in their design.

• Superscalar Out-of-Order CPUs, on the other end, provide extreme flexibility, full programmability, and reasonable performance across various workloads. However, they require large area and energy overheads for a given performance, use memory inefficiently, and are often hard to scale well to manycore systems.

• GPUs are parallel and data-oriented by design, yet still meaningfully programmable, aiming for a sweet-spot between scalability, efficiency, and programmability. However, are still subject to memory access challenges and often require manual memory management for decent performance.

How can we further improve on these existing paradigms? Can we design decently efficient and performant, yet freely programmable systems with scalable, performant memory systems?

If these questions sound intriguing to you, consider joining us for a project or thesis! You can find currently available projects and our contact information below.

Our Activities

We are primarily interested in architecture design and hardware implementation for high-performance systems. However, ensuring high performance requires us to consider the entire hardware-software stack:

• HPC Software: Design and porting of high-performance applications, benchmarks, compiler tools, and operating systems (Linux) to our hardware.
• Hardware-software codesign: Design of performance-aware algorithms and kernels and hardware that can be efficiently programmed for use in processor-based systems.
• Architecture: RTL implementation of energy-efficient designs with an emphasis on high utilization and throughput, as well as on efficient interoperability with existing IPs.
• SoC design and Implementation: Design of full high-performance systems-on-chips; implementation and tapeout on modern silicon technologies such as TSMC's 65 nm and GlobalFoundries' 22 nm nodes.
• IC testing and Board-Level design: Testing of the returning chips with industry-grade automated test equipment (ATE) and design of system-level demonstrator boards.

Our current interests include systems with low control-to-compute ratios, high-performance on-chip interconnects, and scalable many-core systems. However, we are always happy to explore new domains; if you have an interesting idea, contact us and we can discuss it in detail!

Who are we

Paul Scheffler e-mail: paulsc@iis.ee.ethz.ch phone: +41 44 632 09 15 office: ETZ J85

Thomas Benz e-mail: tbenz@iis.ee.ethz.ch phone: +41 44 632 05 18 office: ETZ J85

Nils Wistoff e-mail: nwistoff@iis.ee.ethz.ch phone: +41 44 632 06 75 office: ETZ J85

Matteo Perotti e-mail: mperotti@iis.ee.ethz.ch phone: +41 44 632 05 25 office: ETZ J85

Samuel Riedel e-mail: sriedel@iis.ee.ethz.ch phone: +41 44 632 65 69 office: ETZ J71.2

Matheus Cavalcante e-mail: matheusd@iis.ee.ethz.ch phone: +41 44 632 54 96 office: ETZ J69.2

Andreas Kurth e-mail: akurth@iis.ee.ethz.ch phone: +41 44 632 04 87 office: ETZ J69.2

Florian Zaruba e-mail: zarubaf@iis.ee.ethz.ch phone: +41 44 632 65 56 office: ETZ J89

Fabian Schuiki e-mail: fschuiki@iis.ee.ethz.ch phone: +41 44 632 67 89 office: ETZ J89

Projects

Available Projects

• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
• Efficient Synchronization of Manycore Systems (M/1S)
• Evaluating memory access pattern specializations in OoO, server-grade cores (M)
• Hypervisor Extension for Ariane (M)
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• IP-Based SoC Generation and Configuration (1-3S/B)
• Manycore System on FPGA (M/S/G)
• Physical Implementation of Ara, PULP's Vector Machine (1-2S)
• RISC-V base ISA for ultra-low-area cores (2-3G)
• SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
• Transforming MemPool into a CGRA (M)

Projects In Progress

• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• ISA extensions in the Snitch Processor for Signal Processing (M)
• LLVM and DaCe for Snitch (1-2S)
• Multi issue OoO Ariane Backend (M)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)

Completed Projects

• A Snitch-based Compute Accelerator for HERO (M/1-2S)
• MemPool on HERO (1S)

Reserved Projects