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Showing below up to 156 results in range #1 to #156.

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  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. 3D Turbo Decoder ASIC Realization
  3. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
  4. ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
  5. ASIC implementation of an interpolation-based wideband massive MIMO detector
  6. A Post-Simulation Trace-Based RISC-V GDB Debugging Server
  7. A Snitch-based Compute Accelerator for HERO
  8. A Trustworthy Three-Factor Authentication System
  9. Acceleration and Transprecision
  10. All-Digital In-Memory Processing
  11. An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
  12. AnalogInt
  13. Analog IC Design
  14. Andrea Cossettini
  15. Andreas Kurth
  16. Application Specific Frequency Synthesizers (Analog/Digital PLLs)
  17. Audio
  18. Audio Signal Processing
  19. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
  20. Beamspace processing for 5G mmWave massive MIMO on GPU
  21. Benchmarking a heterogeneous 217-core MPSoC on HPC applications
  22. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
  23. Benjamin Sporrer
  24. Benjamin Weber
  25. Biomedical System on Chips
  26. Biomedical Systems on Chip
  27. Channel Estimation and Equalization for LTE Advanced
  28. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
  29. Characterization techniques for silicon photonics-Lumiphase
  30. Charge and heat transport through graphene nanoribbon based devices
  31. Christoph Keller
  32. Christoph Leitner
  33. Coding Guidelines
  34. Completed
  35. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
  36. Cryptography
  37. DaCe on Snitch
  38. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  39. Design Review
  40. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
  41. Design and implementation of the front-end for a portable ionizing radiation detector
  42. Design of a D-Band Variable Gain Amplifier for 6G Communication
  43. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
  44. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
  45. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
  46. Development of an efficient algorithm for quantum transport codes
  47. Digital Transmitter for Mobile Communications
  48. Efficient Banded Matrix Multiplication for Quantum Transport Simulations
  49. Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening
  50. Electrothermal characterization of van der Waals Heterostructures with a partial overlap
  51. Embedded Artificial Intelligence:Systems And Applications
  52. Embedded Systems and autonomous UAVs
  53. Enabling Standalone Operation
  54. Every individual on the planet should have a real chance to obtain personalized medical therapy
  55. Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
  56. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  57. FPGA-Based Digital Frontend for 3G Receivers
  58. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  59. Fabian Schuiki
  60. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  61. Federico Villani
  62. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  63. Final Presentation
  64. Final Report
  65. Frank K. Gürkaynak
  66. GRAND Hardware Implementation
  67. Guillaume Mocquard
  68. Harald Kröll
  69. Hardware Accelerated Derivative Pricing
  70. Herschmi
  71. High resolution, low power Sigma Delta ADC
  72. Hyperdimensional Computing
  73. IBM A2O Core
  74. IBM Research–Zurich
  75. IP-Based SoC Generation and Configuration (1-3S)
  76. ISA extensions in the Snitch Processor for Signal Processing (1M)
  77. IcySoC
  78. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  79. Implementation of a Heterogeneous System for Image Processing on an FPGA
  80. Influence of the Initial Filament Geometry on the Forming Step in CBRAM
  81. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
  82. Integrated Devices, Electronics, And Systems
  83. Integrated silicon photonic structures
  84. Integrated silicon photonic structures-Lumiphase
  85. Integrating Hardware Accelerators into Snitch
  86. Investigation of Metal Diffusion in Oxides for CBRAM Applications
  87. Investigation of Redox Processes in CBRAM
  88. Jammer-Resilient Synchronization for Wireless Communications
  89. Jammer Mitigation Meets Machine Learning
  90. Karim Badawi
  91. Libria
  92. LightProbe
  93. Low-Power Time Synchronization for IoT Applications
  94. Low Power Embedded Systems
  95. Low Power Embedded Systems and Wireless Sensors Networks
  96. Machine Learning Assisted Direct Synthesis of Passive Networks
  97. Mapping Networks on Reconfigurable Binary Engine Accelerator
  98. Marco Bertuletti
  99. Matheus Cavalcante
  100. Matteo Perotti
  101. Matthias Korb
  102. Mattia
  103. Mauro Salomon
  104. MemPool on HERO
  105. Michael Muehlberghuber
  106. Michael Rogenmoser
  107. Mixed-Signal Circuit Design
  108. Mixed Signal IC Design
  109. Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
  110. Moritz Schneider
  111. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
  112. Near-Memory Training of Neural Networks
  113. Neural Processing
  114. Nils Wistoff
  115. Noise Figure Measurement for Cryogenic System
  116. Norbert Felber
  117. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
  118. Optimal System Duty Cycling
  119. PULP
  120. Palm size chip NMR
  121. Pascal Hager
  122. Philipp Schönle
  123. Pirmin Vogel
  124. Positioning with Wireless Signals
  125. Prasadar
  126. Project Meetings
  127. Project Plan
  128. Quantum Transport Modeling of Interband Cascade Lasers (ICL)
  129. Quantum transport in 2D heterostructures
  130. Real-Time Optimization
  131. Reconfigurable Fully-Unrolled 2D-FFT Core Generator for Multi-Antenna mmWave Communication
  132. Research
  133. Robert Balas
  134. SSR combined with FREP in LLVM/Clang
  135. Signal to Noise Ratio Estimation for 3G standards
  136. Simulation of 2D artificial cilia metasurface in COMSOL
  137. Simultaneous Sensing and Communication
  138. Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)
  139. Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)
  140. Software
  141. Stefan Lippuner
  142. Stefan Mach
  143. Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets
  144. Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
  145. Super Resolution Radar/Imaging at mm-Wave frequencies
  146. Taimir Aguacil
  147. Tbenz
  148. Telecommunications
  149. Test page
  150. Test project
  151. Theory, Algorithms, and Hardware for Beyond 5G
  152. Time Synchronization for 3G Mobile Communications
  153. Unconventional phase change memory device concepts for in-memory and neuromorphic computin
  154. VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
  155. Versatile HW SW Digital PHY for inter chip communication
  156. Weekly Reports

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