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Showing below up to 250 results in range #201 to #450.
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- Cycle-Accurate Event-Based Simulation of Snitch Core (9 categories)
- Integrating Hardware Accelerators into Snitch (1S) (9 categories)
- On-Device Learnable Embeddings for Acoustic Environments (9 categories)
- HERO: TLB Invalidation (9 categories)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (9 categories)
- Knowledge Distillation for Embedded Machine Learning (9 categories)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (9 categories)
- Outdoor Precision Object Tracking for Rockfall Experiments (9 categories)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (9 categories)
- Deep neural networks for seizure detection (9 categories)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S) (9 categories)
- EEG artifact detection for epilepsy monitoring (9 categories)
- Trace Debugger for custom RISC-V Core (9 categories)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (9 categories)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (9 categories)
- AXI-based Network on Chip (NoC) system (9 categories)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (9 categories)
- EEG artifact detection with machine learning (9 categories)
- On - Device Continual Learning for Seizure Detection on GAP9 (9 categories)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (9 categories)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) (9 categories)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B) (9 categories)
- Writing a Hero runtime for EPAC (1-3S/B) (9 categories)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (9 categories)
- Investigation of Quantization Strategies for Retentive Networks (1S) (9 categories)
- BLISS - Battery-Less Identification System for Security (9 categories)
- Hardware/software codesign neural decoding algorithm for “neural dust” (9 categories)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (9 categories)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (9 categories)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (9 categories)
- Flexfloat DL Training Framework (9 categories)
- Active-Set QP Solver on FPGA (9 categories)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (9 categories)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (9 categories)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (9 categories)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (9 categories)
- Ultrasound signal processing acceleration with CUDA (9 categories)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (9 categories)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (9 categories)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) (9 categories)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (9 categories)
- ASIC Development of 5G-NR LDPC Decoder (9 categories)
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B) (9 categories)
- NVDLA meets PULP (9 categories)
- Exploring NAS spaces with C-BRED (9 categories)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (9 categories)
- Adding Linux Support to our DMA Engine (1-2S/B) (9 categories)
- NeuroSoC RISC-V Component (M/1-2S) (9 categories)
- Extreme-Edge Experience Replay for Keyword Spotting (9 categories)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M) (9 categories)
- An Efficient Compiler Backend for Snitch (1S/B) (9 categories)
- Analog building blocks for mmWave manipulation (8 categories)
- Wearables in Fashion (8 categories)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (8 categories)
- Deep Convolutional Autoencoder for iEEG Signals (8 categories)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (8 categories)
- Digital Control of a DC/DC Buck Converter (8 categories)
- Using Motion Sensors to Support Indoor Localization (8 categories)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX (8 categories)
- Autonomous Sensing For Trains In The IoT Era (8 categories)
- TCNs vs. LSTMs for Embedded Platforms (8 categories)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (8 categories)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (8 categories)
- Ibex: FPGA Optimizations (8 categories)
- Standard Cell Compatible Memory Array Design (8 categories)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (8 categories)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (8 categories)
- RedCap-5G for IOT application on prototype taped-out silicon (8 categories)
- New RVV 1.0 Vector Instructions for Ara (8 categories)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems (8 categories)
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices (8 categories)
- 3D Matrix Multiplication Unit for ITA (1S) (8 categories)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments (8 categories)
- Event-Driven Vision on an embedded platform (8 categories)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (8 categories)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (8 categories)
- Digital Transmitter for Mobile Communications (8 categories)
- Efficient NB-IoT Uplink Design (8 categories)
- A Wearable System To Control Phone And Electronic Device Without Hands (8 categories)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (8 categories)
- Hardware Exploration of Shared-Exponent MiniFloats (M) (8 categories)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) (8 categories)
- High-throughput Embedded System For Neurotechnology in collaboration with INI (8 categories)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (8 categories)
- Deep Learning for Brain-Computer Interface (8 categories)
- SmartRing (8 categories)
- Towards global Brain-Computer Interfaces (8 categories)
- VLSI Implementation of a 5G Ciphering Accelerator (8 categories)
- RVfplib (8 categories)
- Designing a Power Management Unit for PULP SoCs (8 categories)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (8 categories)
- Accelerator for Boosted Binary Features (8 categories)
- Extended Verification for Ara (8 categories)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M) (8 categories)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras (8 categories)
- Radiation Testing of a PULP ASIC (8 categories)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (8 categories)
- Android reliability governor (8 categories)
- DC-DC Buck converter in 65nm CMOS (8 categories)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (8 categories)
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (8 categories)
- FPGA-Based Digital Frontend for 3G Receivers (8 categories)
- Compiler Profiling and Optimizing (8 categories)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (8 categories)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 categories)
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores (8 categories)
- Wireless Sensing With Long Range Comminication (LoRa) (8 categories)
- PREM Intervals and Loop Tiling (8 categories)
- Real-time View Synthesis using Image Domain Warping (8 categories)
- DMA Streaming Co-processor (8 categories)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 categories)
- Energy Efficient AXI Interface to Serial Link Physical Layer (8 categories)
- Extending our FPU with Internal High-Precision Accumulation (M) (8 categories)
- Low-Dropout Regulators for Magnetic Resonance Imaging (8 categories)
- RazorEDGE: An Evolved EDGE DBB ASIC (8 categories)
- Thermal Control of Mobile Devices (8 categories)
- Low Precision Ara for ML (8 categories)
- Efficient TNN compression (8 categories)
- A Wireless Sensor Network for a Smart Building Monitor and Control (8 categories)
- Ultra-wideband Concurrent Ranging (8 categories)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (8 categories)
- Precise Ultra-low-power Timer (8 categories)
- Real-time eye movement analysis on a tablet computer (8 categories)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 categories)
- Short Range Radars For Biomedical Application (8 categories)
- Integration Of A Smart Vision System (8 categories)
- LightProbe - CNN-Based-Image-Reconstruction (8 categories)
- Mapping Networks on Reconfigurable Binary Engine Accelerator (8 categories)
- Ultrasound image data recycler (8 categories)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning (8 categories)
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles (8 categories)
- Smart Patch For Heath Care And Rehabilitation (8 categories)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (8 categories)
- Transformer Deployment on Heterogeneous Many-Core Systems (8 categories)
- Physical Implementation of ITA (2S) (8 categories)
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE (8 categories)
- Efficient collective communications in FlooNoC (1M) (8 categories)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (8 categories)
- Extending the RISCV backend of LLVM to support PULP Extensions (8 categories)
- Bluetooth Low Energy receiver in 65nm CMOS (8 categories)
- Edge Computing for Long-Term Wearable Biomedical Systems (8 categories)
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (8 categories)
- All the flavours of FFT on MemPool (1-2S/B) (8 categories)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M) (8 categories)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S) (8 categories)
- Indoor Positioning with Bluetooth (8 categories)
- Spiking Neural Network for Autonomous Navigation (8 categories)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 categories)
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion (8 categories)
- Predictable Execution on GPU Caches (8 categories)
- LightProbe - Frontend Firmware and Control Side Channel (8 categories)
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration (8 categories)
- FPGA System Design for Computer Vision with Convolutional Neural Networks (8 categories)
- PVT Dynamic Adaptation in PULPv3 (8 categories)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (8 categories)
- Triple-Core PULPissimo (8 categories)
- Novel Metastability Mitigation Technique (8 categories)
- Open Power-On Chip Controller Study and Integration (8 categories)
- Securing Block Ciphers against SCA and SIFA (8 categories)
- Indoor Smart Tracking of Hospital instrumentation (8 categories)
- Time Synchronization for 3G Mobile Communications (8 categories)
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications (8 categories)
- Zero Power Touch Sensor and Reciever For Body Communication (8 categories)
- PULP-Shield for Autonomous UAV (8 categories)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (8 categories)
- LightProbe - Implementation of compressed-sensing algorithms (8 categories)
- Bringing XNOR-nets (ConvNets) to Silicon (8 categories)
- Compression of iEEG Data (8 categories)
- Runtime partitioning of L1 memory in Mempool (M) (8 categories)
- Improved Reacquisition for the 5G Cellular IoT (8 categories)
- System Emulation for AR and VR devices (8 categories)
- Vector Processor for In-Memory Computing (8 categories)
- Ibex: Bit-Manipulation Extension (7 categories)
- Self-Learning Drones based on Neural Networks (7 categories)
- Design of Scalable Event-driven Neural-Recording Digital Interface (7 categories)
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders (7 categories)
- Time and Frequency Synchronization in LTE Cat-0 Devices (7 categories)
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams (7 categories)
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers (7 categories)
- Interference Cancellation for EC-GSM-IoT (7 categories)
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip (7 categories)
- LightProbe - Thermal-Power aware on-head Beamforming (7 categories)
- Towards The Integration of E-skin into Prosthetic Devices (7 categories)
- Design of low mismatch DAC used for VAD (7 categories)
- Low-power Temperature-insensitive Timer (7 categories)
- Efficient Implementation of an Active-Set QP Solver for FPGAs (7 categories)
- Turbo Equalization for Cellular IoT (7 categories)
- Virtual Memory Ara (7 categories)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich) (7 categories)
- Implementation of an AES Hardware Processing Engine (B/S) (7 categories)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (7 categories)
- Visualization of Neural Architecture Search Spaces (7 categories)
- Exploring schedules for incremental and annealing quantization algorithms (7 categories)
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems (7 categories)
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) (7 categories)
- 3D Turbo Decoder ASIC Realization (7 categories)
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich) (7 categories)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing (7 categories)
- Network-off-Chip (M) (7 categories)
- Audio Visual Speech Recognition (1S/1M) (7 categories)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (7 categories)
- Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision (7 categories)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core (7 categories)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (7 categories)
- Next Generation Channel Decoder (7 categories)
- Low Power Geolocalization And Indoor Localization (7 categories)
- An Industrial-grade Bluetooth LE Mesh Network Solution (7 categories)
- Channel Estimation for TD-HSPA (7 categories)
- Real-Time Stereo to Multiview Conversion (7 categories)
- Development of an implantable Force sensor for orthopedic applications (7 categories)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (7 categories)
- Network-on-Chip for coherent and non-coherent traffic (M) (7 categories)
- Audio Visual Speech Separation (1S/1M) (7 categories)
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation (7 categories)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (7 categories)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (7 categories)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (7 categories)
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC (7 categories)
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE (7 categories)
- Low Power Neural Network For Multi Sensors Wearable Devices (7 categories)
- Evolved EDGE Physical Layer Incremental Redundancy Architecture (7 categories)
- Wake Up Radio For Energy Efficient Communication System and IC Design (7 categories)
- Serverless Benchmarks on RISC-V (M) (7 categories)
- Towards Autonomous Navigation for Nano-Blimps (7 categories)
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces (7 categories)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction (7 categories)
- Audio Visual Speech Separation and Recognition (1S/1M) (7 categories)
- Implementing A Low-Power Sensor Node Network (7 categories)
- Fast Wakeup From Deep Sleep State (7 categories)
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications (7 categories)
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP (7 categories)
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor (7 categories)
- A Recurrent Neural Network Speech Recognition Chip (7 categories)
- Evaluating An Ultra low Power Vision Node (7 categories)
- Hardware/software co-programming on the Parallella platform (7 categories)
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design (7 categories)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) (7 categories)
- Bluetooth Low Energy network with optimized data throughput (7 categories)
- Putting Together What Fits Together - GrÆStl (7 categories)
- Rethinking our Convolutional Network Accelerator Architecture (7 categories)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture (7 categories)
- Scan Chain Fault Injection in a PULP SoC (1S) (7 categories)
- Realtime Gaze Tracking on Siracusa (7 categories)
- Implementation of a Coherent Application-Class Multicore System (1-2S) (7 categories)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities (7 categories)
- MatPHY: An Open-Source Physical Layer Development Framework (7 categories)
- Energy Efficient Serial Link (7 categories)
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces (7 categories)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) (7 categories)
- Bandwidth Efficient NEureka (7 categories)
