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• Modular Spiking Neural Network Accelerator
  #REDIRECT [[Event-Driven Convolutional Neural Network Modular Accelerator]]
  75 bytes (7 words) - 09:36, 5 August 2020
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
  <!-- (M/1-2S): A Snitch-based Compute Accelerator for HERO --> ...xchangeable. HERO features a shared virtual memory system between host and accelerator and provides a heterogeneous compiler toolchain with OpenMP support for acc
  11 KB (1,617 words) - 23:59, 6 February 2021
• VLSI Implementation of a 5G Ciphering Accelerator
  ...ng the low-latency demands for URLLC. In a second part of the project, the accelerator architecture will be ported to HDL and an ASIC implementation will be deriv
  3 KB (404 words) - 10:05, 9 February 2021
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  <!-- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) --> This thesis' goal is to develop a small and energy vector accelerator unit, and integrate it with MemPool.
  11 KB (1,609 words) - 10:00, 30 June 2022
• Fast Accelerator Context Switch for PULP
  <!-- Fast Accelerator Context Switch For PULP --> ...troller core with a cluster of eight RISC-V cores used as accelerator. The accelerator needs a better mechanism to manage its state for context switching.]]
  6 KB (835 words) - 16:27, 7 July 2023
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
  <!-- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1 [[File:maddness_floorplan.png|thumb|350px|Floorplan or the Maddness Accelerator.]]
  6 KB (846 words) - 16:50, 3 November 2022
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
  <!-- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1 ...:maddness_floorplan.png|thumb|350px|Figure 1: Clock layout of the MADDness accelerator using ASAP7 technology]]
  6 KB (823 words) - 16:32, 3 November 2022
• Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
  ...(VMMs), and digital tiles to handle intermediate digital operations. This accelerator is capable of performing inference at significantly lower latencies and wit
  3 KB (356 words) - 14:53, 11 October 2023
• Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture
  #REDIRECT [[Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)]]
  110 bytes (11 words) - 10:31, 28 August 2023
• Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
  * 40% Implementing Snitch-based in-network accelerator, creating SsPIN ...er Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. "A RISC-V in-network accelerator for flexible high-performance low-power packet processing." 2021 ACM/IEEE 4
  3 KB (374 words) - 10:24, 3 November 2023
• A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
  <!-- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) -->
  3 KB (342 words) - 13:02, 12 February 2024
• A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks
  #REDIRECT [[A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)]]
  100 bytes (13 words) - 11:05, 2 November 2023
• Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
  ...reating Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --> ...dedicated special-purpose buffer. Our idea is to create such a reshuffling accelerator (inside of iDMA) using the already present cluster TCDM as its buffer.
  2 KB (314 words) - 10:27, 3 November 2023
• Implementation of an Accelerator for Retentive Networks (1-2S)
  <!-- Implementation of an Accelerator for Retentive Networks (M/1-2S) --> In this project, we aim to lay the foundation for a retention accelerator that is able to execute the main layers in Retentive Networks with little t
  5 KB (735 words) - 14:31, 18 February 2024
• Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
  <!-- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) --> ...ce with its 96 Tensix cores (each containing 5 RISC-V processors, a tensor accelerator, a vector co-processor and up to 1.5MB of SRAM). The Grayskull card comes w
  3 KB (459 words) - 13:24, 12 April 2024

Page text matches

• Efficient Implementation of an Active-Set QP Solver for FPGAs
  ...ystem integration aspects. Eventually, the goal is to attach the developed accelerator to the ARM processing system on the Xilinx Zynq platform, and establish the [[Category:Digital]] [[Category:Master Thesis]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Cont
  4 KB (542 words) - 12:39, 1 June 2017
• Design of State Retentive Flip-Flops
  ...ate. While this is acceptable for some sub-circuits, like a small hardware accelerator with no relevant information to be retained between two calls, it is not ac
  2 KB (364 words) - 09:34, 25 July 2017
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  ...e have several aspects which we would like to explore: porting the Origami accelerator to run efficiently on the FPGA, hardware/software-co-design configuring mem ...Mayer, S. Willi, B. Muheim, L. Benini, “Origami: A Convolutional Network Accelerator,” in Proceedings of the 25th Edition on Great Lakes Symposium on VLSI, 20
  3 KB (397 words) - 18:17, 29 August 2016
• Rethinking our Convolutional Network Accelerator Architecture
  ...e time is spent performing the convolutions (80% to 90%). We have built an accelerator for this, Origami, which has been very successful. Nevertheless, it has som ...Samuel Willi, Beat Muheim, Luca Benini, "Origami: A Convolutional Network Accelerator", Proc. ACM/IEEE GLS-VLSI'15 [http://dl.acm.org/citation.cfm?id=2743766] [h
  9 KB (1,263 words) - 18:52, 12 December 2016
• A Hardware Architecture for Real-Time Saliency Estimation
  #REDIRECT [[Accelerator for Spatio-Temporal Video Filtering]]
  61 bytes (6 words) - 18:44, 14 April 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...running on the host CPU [1,2] and a dedicated helper thread running on the accelerator [3]. The first IOTLB is implemented using a fully-associative content addre ...ns through, e.g., an mmap() system call. Ideally, all data shared with the accelerator is placed in this section, requiring a single entry in the first IOTLB only
  6 KB (866 words) - 13:43, 29 November 2019
• Bringing XNOR-nets (ConvNets) to Silicon
  ...hem better and use their structure to build an even more efficient ConvNet accelerator with almost no multipliers and relatively small adders. ...Benini, L. (2016). YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights. arXiv preprint arXiv:1606.05487. [https://arxiv.or
  10 KB (1,357 words) - 16:25, 30 October 2020
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...field of active exciting research to develop a state-of-art neuromorphic accelerator for MPSoC and FPGA targets. You will learn:
  9 KB (1,427 words) - 18:36, 5 September 2019
• Single-Bit-Synapse Spiking Neural System-on-Chip
  ...field of active exciting research to develop a state-of-art neuromorphic accelerator for MPSoC and FPGA targets. You will learn:
  7 KB (1,000 words) - 12:22, 13 January 2017
• PULP-Shield for Autonomous UAV
  ...directly connected to the Himax ULP camera [7] and a second connecting the accelerator to the existing MCU. ...Palossi, A. Marongiu, D. Rossi and L. Benini, "Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms," 2016 Design, Automatio
  6 KB (875 words) - 11:06, 23 February 2018
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  ...and Luca Benini. "YodaNN: An ultra-low power convolutional neural network accelerator based on binary weights." In VLSI (ISVLSI), 2016 IEEE Computer Society Annu
  6 KB (823 words) - 08:36, 20 January 2021
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  In this thesis, the students will develop an optimized Deconvolution Accelerator which can be used to implement state-of-the-art neural networks with a deco
  6 KB (842 words) - 08:37, 20 January 2021
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...n a field of active exciting research to develop a state-of-art inference accelerator for MPSoC and FPGA targets. You will learn:
  6 KB (949 words) - 13:41, 10 November 2020
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
  ...nstitute of Neuroinformatics designed '''''NullHop''''' [Aimar2017], a CNN accelerator architecture which can support the implementation of state of the art CNNs ...mar2017] A. Aimar et al., NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps [https://arxiv.org/pdf/1706
  7 KB (1,001 words) - 10:43, 26 June 2017
• BigPULP: Multicluster Synchronization Extensions
  ...-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integrati ...oading of highly-parallel OpenMP function kernels from the host CPU to the accelerator [2], and
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integrati ...oading of highly-parallel OpenMP function kernels from the host CPU to the accelerator [2], and
  6 KB (801 words) - 15:05, 23 August 2018
• Smart Virtual Memory Sharing
  The main difficulty in traditional accelerator programming stems from a widely coherent caches and virtual memory. The accelerator features local, private
  6 KB (865 words) - 12:16, 17 November 2017
• Zksnark
  #REDIRECT [[Elliptic Curve Accelerator for zkSNARKS]]
  53 bytes (6 words) - 09:54, 24 August 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  #If interested: Commissioning of the unit in particle accelerator beam line experiment at PSI
  4 KB (460 words) - 21:42, 30 January 2018
• HERO: TLB Invalidation
  ...-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integrati ...oading of highly-parallel OpenMP function kernels from the host CPU to the accelerator [2], and
  6 KB (796 words) - 17:19, 18 November 2019

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