User contributions
From iis-projects
- 18:47, 24 November 2023 diff hist -1 Taping a Safer Silicon Implementation of Snitch (M/2-3S) current
- 11:18, 3 November 2023 diff hist +2,414 N Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) Created page with "<!-- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) --> Category:Digital Category:High Performance SoCs [..." current
- 10:53, 3 November 2023 diff hist -19 Taping a Safer Silicon Implementation of Snitch (M/2-3S) →Status: Available
- 10:52, 3 November 2023 diff hist +2,237 N Taping a Safer Silicon Implementation of Snitch (M/2-3S) Created page with "<!-- Creating Taping a Safer Silicon Implementation of Snitch (M/2-3S) (1-3S/B/2-3G) --> Category:Digital Category:ASIC Category:High Performance SoCs Category:..."
- 10:27, 3 November 2023 diff hist +2,332 N Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) Created page with "<!-- Creating Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:C..." current
- 10:25, 3 November 2023 diff hist -2,461 Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) Blanked the page current
- 10:24, 3 November 2023 diff hist +162 Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) →Project current
- 10:21, 3 November 2023 diff hist 0 Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- 10:21, 3 November 2023 diff hist 0 Towards Formal Verification of the iDMA Engine (1-3S/B) current
- 10:21, 3 November 2023 diff hist +78 Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- 10:19, 3 November 2023 diff hist 0 IP-Based SoC Generation and Configuration (1-3S/B) current
- 09:55, 3 November 2023 diff hist -1 Creating A Boundry Scan Generator (1-3S/B/2-3G) current
- 09:46, 3 November 2023 diff hist +137 Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) →Introduction
- 09:45, 3 November 2023 diff hist +68 Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) →Project
- 09:44, 3 November 2023 diff hist +81 Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) →Introduction
- 09:39, 3 November 2023 diff hist 0 Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) current
- 09:38, 3 November 2023 diff hist 0 Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) current
- 09:38, 3 November 2023 diff hist 0 Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) current
- 09:36, 3 November 2023 diff hist 0 Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) current
- 09:36, 3 November 2023 diff hist 0 Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) current
- 09:36, 3 November 2023 diff hist 0 Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) current
- 09:35, 3 November 2023 diff hist 0 Extension and Evaluation of TinyDMA (1-2S/B/2-3G) current
- 09:34, 3 November 2023 diff hist +5,474 N Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) Created page with "<!-- Design of an Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) --> Category:Digital Category:High Performance SoCs Category:Comp..."