Pages with the most revisions
From iis-projects
Showing below up to 50 results in range #101 to #150.
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- HW/SW Safety and Security (14 revisions)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (14 revisions)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (14 revisions)
- Finite Element Simulations of Transistors for Quantum Computing (14 revisions)
- High-speed Scene Labeling on FPGA (14 revisions)
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC (13 revisions)
- MatPHY: An Open-Source Physical Layer Development Framework (13 revisions)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (13 revisions)
- Level Crossing ADC For a Many Channels Neural Recording Interface (13 revisions)
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT (13 revisions)
- Shared Correlation Accelerator for an RF SoC (13 revisions)
- On-Board Software for PULP on a Satellite (13 revisions)
- Efficient collective communications in FlooNoC (1M) (13 revisions)
- A Wireless Sensor Network for a Smart LED Lighting control (13 revisions)
- Turbo Equalization for Cellular IoT (13 revisions)
- Cycle-Accurate Event-Based Simulation of Snitch Core (13 revisions)
- Towards global Brain-Computer Interfaces (13 revisions)
- Integrated silicon photonic structures (13 revisions)
- Gomeza old project1 (13 revisions)
- ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G (13 revisions)
- GUI-developement for an action-cam-based eye tracking device (13 revisions)
- Deep Learning for Brain-Computer Interface (13 revisions)
- Online Learning of User Features (1S) (13 revisions)
- On-chip clock synthesizer design and porting (13 revisions)
- Acceleration and Transprecision (13 revisions)
- CLIC for the CVA6 (13 revisions)
- LAPACK/BLAS for FPGA (13 revisions)
- Neural Recording Interface and Signal Processing (13 revisions)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (12 revisions)
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex (12 revisions)
- Peak-to-average power Reduction (12 revisions)
- Sensor Fusion for Rockfall Sensor Node (12 revisions)
- ASIC implementation of an interpolation-based wideband massive MIMO detector (12 revisions)
- Deep neural networks for seizure detection (12 revisions)
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems (12 revisions)
- Stand-Alone Edge Computing with GAP8 (12 revisions)
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems (12 revisions)
- Image and Video Processing (12 revisions)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture (12 revisions)
- PULPonFPGA: Hardware L2 Cache (12 revisions)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (12 revisions)
- Investigation of Quantization Strategies for Retentive Networks (1S) (12 revisions)
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials (12 revisions)
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control (12 revisions)
- BigPULP: Multicluster Synchronization Extensions (12 revisions)
- SmartRing (12 revisions)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (12 revisions)
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device (12 revisions)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device (12 revisions)
- Investigation of Redox Processes in CBRAM (12 revisions)
