Pages with the fewest revisions
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Showing below up to 50 results in range #501 to #550.
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- Novel Metastability Mitigation Technique (6 revisions)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (6 revisions)
- MemPool on HERO (1S) (6 revisions)
- Self Aware Epilepsy Monitoring (6 revisions)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (6 revisions)
- FPGA Optimizations of Dense Binary Hyperdimensional Computing (6 revisions)
- Implementing Configurable Dual-Core Redundancy (6 revisions)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S) (6 revisions)
- Channel Estimation for 3GPP TD-SCDMA (6 revisions)
- System Emulation for AR and VR devices (6 revisions)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (6 revisions)
- Enabling Efficient Systolic Execution on MemPool (M) (6 revisions)
- LightProbe - Ultracompact Power Supply PCB (6 revisions)
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA) (6 revisions)
- IBM Research–Zurich (6 revisions)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (6 revisions)
- VLSI Design of an Asynchronous LDPC Decoder (6 revisions)
- Switched Capacitor Based Bandgap-Reference (6 revisions)
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA (6 revisions)
- CMOS power amplifier for field measurements in MRI systems (6 revisions)
- Change-based Evaluation of Convolutional Neural Networks (6 revisions)
- FPGA mapping of RPC DRAM (6 revisions)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (6 revisions)
- Beat Cadence (6 revisions)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (6 revisions)
- Autonomous Smart Watches: Hardware and Software Desing (6 revisions)
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) (6 revisions)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Putting Together What Fits Together - GrÆStl (7 revisions)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Predictable Execution (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- EEG earbud (7 revisions)
- IoT Turbo Decoder (7 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (7 revisions)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- Compressed Sensing for Wireless Biosignal Monitoring (7 revisions)
- Internet of Things Network Synchronizer (7 revisions)
- Fault Tolerance (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (7 revisions)
- Outdoor Precision Object Tracking for Rockfall Experiments (7 revisions)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (7 revisions)
- Gomeza old project5 (7 revisions)
