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Showing below up to 50 results in range #601 to #650.
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- Fast Wakeup From Deep Sleep State (8 revisions)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- Hypervisor Extension for Ariane (M) (8 revisions)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
- NVDLA meets PULP (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Deep Convolutional Autoencoder for iEEG Signals (8 revisions)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (8 revisions)
- Modular Distributed Data Collection Platform (8 revisions)
- Development of a fingertip blood pressure sensor (8 revisions)
- Pirmin Vogel (8 revisions)
- Multi issue OoO Ariane Backend (M) (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- PREM Runtime Scheduling Policies (8 revisions)
- Weekly Reports (8 revisions)
- A computational memory unit using phase-change memory devices (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format (8 revisions)
- Fault-Tolerant Floating-Point Units (M) (8 revisions)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- BCI-controlled Drone (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- ASIC Implementation of Jammer Mitigation (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- Hardware/software co-programming on the Parallella platform (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- Real-time View Synthesis using Image Domain Warping (9 revisions)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (9 revisions)
- Freedom from Interference in Heterogeneous COTS SoCs (9 revisions)
- Gomeza old project2 (9 revisions)
- A Multiview Synthesis Core in 65 nm CMOS (9 revisions)
- Design and Implementation of an Approximate Floating Point Unit (9 revisions)
