Difference between revisions of "Category:Completed"
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+ | ==Nano TCAD== | ||
+ | ===2013=== | ||
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Revision as of 14:06, 27 March 2014
These projects have already been completed. You can take a look at the results of the project and learn more.
Contents
Digital
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
Nano TCAD
2013
No pages meet these criteria.
Pages in category "Completed"
The following 61 pages are in this category, out of 286 total.
(previous page) (next page)A
- A computational memory unit using phase-change memory devices
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
- A Recurrent Neural Network Speech Recognition Chip
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- A Trustworthy Three-Factor Authentication System
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for HPC monitoring
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Active-Set QP Solver on FPGA
- Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced 5G Repetition Combining
- Aliasing-Free Wavetable Music Synthesizer
- An Energy Efficient Brain-Computer Interface using Mr.Wolf
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Analog Compute-in-Memory Accelerator Interface and Integration
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASIC Implementation of Jammer Mitigation
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autonomous Sensing For Trains In The IoT Era
B
- Bandwidth Efficient NEureka
- Baseband Meets CPU
- Beamspace processing for 5G mmWave massive MIMO on GPU
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- BigPULP: Multicluster Synchronization Extensions
- BigPULP: Shared Virtual Memory Multicluster Extensions
- Bluetooth Low Energy receiver in 65nm CMOS
- Bridging QuantLab with LPDNN
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
C
- Cell-Free mmWave Massive MIMO Communication
- Change-based Evaluation of Convolutional Neural Networks
- Channel Decoding for TD-HSPA
- Channel Estimation for TD-HSPA
- Charging System for Implantable Electronics
- CLIC for the CVA6
- CMOS power amplifier for field measurements in MRI systems
- Compressed Sensing Reconstruction on FPGA
- Compression of Ultrasound data on FPGA
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- Creating a HDMI Video Interface for PULP