List of redirects
From iis-projects
Showing below up to 50 results in range #21 to #70.
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- Belfanti → User:Belfanti
- Bioprojects → Biomedical Circuits, Systems, and Applications
- Build the Fastest 2G Modem → Build the Fastest 2G Modem Ever
- CLIC for the CVA 6 → CLIC for the CVA6
- Cell Measurements for the Internet of Things → Cell Measurements for the 5G Internet of Things
- Channel Shortening ASIC → Channel Shortening Prefilter
- Channel Shortening Prefilter → VLSI Implementation of a Channel Shortener
- Characterization techniques for silicon photonics → Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Coherence-Capable Write-Back L1 Data Cache for Ariane → Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Configurable Ultra low power LDO → Configurable Ultra Low Power LDO
- Convolutional Network Accelerator → Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Convolutional Neural Networks in Bateryless Nodes → Gomeza old project4
- Cryogenic measurements and modeling of electrical devices → Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- DaCe on Snitch (M/1-3S) → LLVM and DaCe for Snitch (1-2S)
- Deep-Learning Phoneme Recognition from a Ultra-Low Power Spiking Cochlea → Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
- Design and Implementation of a multi-mode multi-master I2C Interface → Design and Implementation of a multi-mode multi-master I2C peripheral
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA → Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design of Charge-Pump PLL in 28nm for 5G communication applications → Design of Charge-Pump PLL in 22nm for 5G communication applications
- Development Of A Test Bed For Ultrasonic Transducer Characterization → Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- Digital Audio High Level Synthesis → Digital Audio High Level Synthesis for FPGAs
- Digital Audio High Level Synthesis for FPGAs → Digital Audio Processor for Cellular Applications
- Digital Beamforming ASIC for 3D Ultrasound Imaging → Digital Beamforming for Ultrasound Imaging
- Digital Front End Design for Narrowband LTE Systems → Time and Frequency Synchronization in LTE Cat-0 Devices
- Digital Transmitter Mobile Communications → Digital Transmitter for Mobile Communications
- EDGE Evolution Protocol Analyzer → Open Source Baseband Firmware for 2G Cellular Networks
- Electrical characterization and optimization of electrochemical random-access memory for analog computing → Phase-change memory devices for emerging computing paradigms
- Electron conductance of lithiated SnO2-based anode materials → Electron conductance of lithiated SnO₂ -based anode materials for Li-ion batteries
- Electron conductance of lithiated SnO₂ -based anode materials for Li-ion batteries → Stable nonvolatile resistance switching (NVRS) in single-layer 2D Materials
- Elliptic Curve Accelerator for zkSNARKS → Elliptic Curve Accelerator for zkSNARKs
- Energy Efficient AXI Inteface → Energy Efficient AXI Inteface to Analog Circuit
- Energy Efficient AXI Inteface to Analog Circuit → Energy Efficient AXI Inteface to serial link physical layer
- Energy Efficient AXI Inteface to Serial Link Physical Layer → Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient AXI Inteface to serial link physical layer → Energy Efficient AXI Inteface to Serial Link Physical Layer
- Energy Efficient Heterogeneous MCU Platforms → Gomeza old project1
- Energy Efficient Heterogeneous Sensor Nodes → Gomeza old project3
- Energy Effiecient Serial Link → Energy Efficient Serial Link
- Energy Netural Multi Sensors Wearable Device → Energy Neutral Multi Sensors Wearable Device
- Energy effiecient serial link → Energy Effiecient Serial Link
- Erg → FPGA mapping of RPC DRAM
- EvaLTE → EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- EvalEDGE → EvalEDGE: A 2G Cellular Transceiver FMC
- Event Driven Spike sorting engine → Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Fast Data Interface → Data Interface: SPI to PC Bridge for ASICs
- Fast Wakeup → Fast Wakeup From Deep Sleep State
- Fault Tolerant OpenPULP System for Critical Spacial Applications → PULP in space - Fault Tolerant PULP System for Critical Space Applications
- First ASIC Realization For A New HSPA/HSPA+ Detector → Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA
- Flexible Electronic Systems and Epidermal Devices → Flexible Electronic Systems and Embedded Epidermal Devices
- GPU-Accelerated Nanoelectronic Device Simulations → Investigation of Redox Processes inCBRAM
- HERO: TLB Coherency → HERO: TLB Invalidation
- Heterogeneous Acceleration Systems → Heterogeneous SoCs
