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• Main Page
  * [[Analog| Analog and Mixed Signal Design]] * [[Design of a D-Band Variable Gain Amplifier for 6G Communication]]
  5 KB (540 words) - 12:31, 8 May 2024
• Template
  : 40% ASIC Design * '''[[Design Review]]'''
  4 KB (397 words) - 15:44, 14 February 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  ...'' for polarization and testing of piezoelectric polymers. It also aims to design the digital architecture in such a way that later studies will allow '''ML- : Analog Mixed Signal Design
  6 KB (741 words) - 18:14, 21 July 2023
• Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  ...distortion) and noise is necessary. For state-of-the-art resolution, fully analog RC oscillators are required. To stabilize their amplitude, a leveling loop : Interest in high-performance mixed signal circuit design;
  2 KB (307 words) - 20:06, 17 February 2015
• Audio DAC Conversion Jitter Measurement System
  : Interest in high-performance mixed signal circuit design : Experience in analog circuit design beneficial
  2 KB (251 words) - 20:06, 17 February 2015
• Analog
  = Analog and Mixed Signal Design Group = The Analog and Mixed Signal Design Group is specialized in designing mixed signal integrated circuits and systems. The group divides into following re
  3 KB (369 words) - 18:11, 1 March 2023
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
  ...ion should also serve as evaluation platform for a later mixed-signal ASIC design. : Some experience in circuit design with discrete active and passive components.
  3 KB (438 words) - 18:06, 3 February 2015
• Receiver design for the DigRF 4G high speed serial link
  The task of this project is to design the receiver front-end architecture of a serial DigRF4G link. This standard : Analog Integrated Circuits
  1 KB (197 words) - 17:37, 21 December 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for : ... Design and implement your own software cache suitable for the heterogeneous platfo
  5 KB (716 words) - 13:43, 29 November 2019
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...ver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units (I This system design project requires work to be done at several layers of abstraction. More pre
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...ver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units (I : ... Implement the selected design in hardware by extending the current design.
  4 KB (554 words) - 17:57, 7 November 2017
• Switched Capacitor Based Bandgap-Reference
  ...re important building blocks in analog and mixed-signal integrated circuit design. The classical Band Gap-Reference combines the negative VBE temperature coe ...is offers the possibility to study main aspects of analog and mixed-signal design, such as noise, linearity, matching, small signal-concepts and power consum
  4 KB (471 words) - 11:13, 3 May 2018
• Compressed Sensing for Wireless Biosignal Monitoring
  ...//asic.ee.ethz.ch/2014/CerebroV4.0_Homer.html] including analog front-end, analog-to-digital conversion, digital signal processing and a compressed sensing e This project may be extended to include the design of a digital ASIC (Application Specific Integrated Circuit) or the implemen
  2 KB (353 words) - 08:35, 20 January 2021
• Low Power Neural Network For Multi Sensors Wearable Devices
  ...ly monitoring the sensor signal. Circuit usually operates in the analog or mixed signal domain, and provides a coarse recognition of some pattern related to ...ise etc.) MEMS microphone is used as an signal input. Prototype implements analog-domain spectral decomposition using multiple band-pass filtering banks. Fre
  7 KB (895 words) - 17:02, 28 July 2017
• PULPonFPGA: Hardware L2 Cache
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for ...mplementation on the Xilinx Virtex-7 FPGA but if desired, an ASIC back-end design can also be implemented.
  5 KB (711 words) - 10:27, 5 November 2019
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for : 20% VHDL/System Verilog, FPGA Design
  5 KB (712 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for [[Category:System Design]]
  6 KB (866 words) - 13:43, 29 November 2019
• Charging System for Implantable Electronics
  Using mixed-signal SoCs developed at IIS it is possible to integrate a system to : Experience with hardware design and embedded software
  3 KB (366 words) - 13:05, 27 April 2018
• On-chip clock synthesizer design and porting
  ...endent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking requirements. All-digital frequency-l ...built and successfully tested various generations of a low-complexity FLL design in different technologies including 65nm and 28nm CMOS technologies.
  3 KB (389 words) - 11:20, 14 September 2016
• BigPULP: Multicluster Synchronization Extensions
  : a mixed hardware/software solution enabling lightweight, shared virtual memory (SVM : 50% Implementation (VHDL, FPGA/ASIC Design, C)
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  : a mixed hardware/software solution enabling lightweight, shared virtual memory (SVM : 50% Implementation (C, VHDL, FPGA/ASIC Design)
  6 KB (801 words) - 15:05, 23 August 2018
• HERO: TLB Invalidation
  : a mixed hardware/software solution enabling lightweight, shared virtual memory (SVM : 50% Design and Implementation (SystemVerilog, C, FPGA/ASIC Design)
  6 KB (796 words) - 17:19, 18 November 2019
• Integrated Information Processing
  rect 1 800 852 1540 [[Analog-to-Information Conversion for Low-Power Sensing]] rect 953 800 1802 1540 [[Mixed-Signal Circuit Design]]
  7 KB (814 words) - 16:53, 8 January 2024
• Biomedical Systems on Chip
  ...Analog and Mixed Signal Design Group we are exploring deep integration of analog precision circuits with the digital processor of the PULP family, both work <ul><li> Analog circuit design and layout for low-power high-precision biomedical applications.</li>
  2 KB (327 words) - 19:55, 22 February 2018
• Brunn test
  = Analog and Mixed Signal Design Group = The Analog and Mixed Signal Design Group is specialized in designing mixed signal integrated circuits and systems. The group divides into following re
  2 KB (311 words) - 12:02, 5 December 2018
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  : Analog Mixed Signal Design : PCB Design
  5 KB (644 words) - 18:18, 21 July 2023
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  ...at comes from over 20 years of experience in mixed-signal neural processor design, advanced neural routing architectures, and neural algorithms. Explore weight-agnostic networks for mixed-signal reservoirs
  5 KB (692 words) - 15:45, 10 November 2020
• Real-Time Motor-Imagery Classification Using Neuromorphic Processor
  * Propose novel low power mixed analog-digital systems for biomedical signal (in particular EEG but suitable also * '''[[Design Review]]'''
  6 KB (815 words) - 20:02, 10 March 2024
• Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
  This requires the design of an analog/mixed-signal board that generates non-overlapping clocks with programmable amplit ...osts the nanoelectrode array biochips. Starting from an existing tentative design, the project will consist in performing the PCB layout and assessing its pe
  5 KB (620 words) - 07:56, 26 May 2020
• Andrea Cossettini
  ...of Udine. His post-​doctoral research focus was on circuits and systems design for biomedical applications, with a special emphasis on [https://iis-projec * Analog/mixed-signal biomedical circuits and systems design
  3 KB (406 words) - 17:17, 3 May 2024
• Biomedical Circuits, Systems, and Applications
  Many research topics are actively ongoing around the human body, from chip design, to system development, to algorithmic investigations in various applicatio ...gy storage units, transistors, and complete integrated circuits (ICs). The design of these systems allows for comfortable wear, as they can be positioned clo
  9 KB (1,292 words) - 19:16, 23 March 2024
• Guillaume Mocquard
  ...of the Nano-TCAD group of Mathieu Luisier). His research targets Analog IC Design for motion correction in Magnetic Resonance Imaging. * Analog IC Design, VCO
  1 KB (143 words) - 17:55, 1 March 2023
• VLSI Implementation of a Systolic Array for LMMSE Detection in mmWave Massive MIMO-OFDM
  ...the ADCs into a single mixed-signal chip [4] that takes the down-converted analog signals from the antennas and produces the symbol estimates, necessitates i ...iu, "Angular-Domain Massive MIMO Detection: Algorithm, Implementation, and Design Tradeoffs," in IEEE Transactions on Circuits and Systems I: Regular Papers,
  6 KB (843 words) - 17:16, 26 September 2023
• High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
  ...itical digital processing. The system will have as input a large number of analog signals of approximatively a GHz of bandwidth, which makes the testing proc ...65nm technology. You will then design the DAC. After having verified your design, layout will be also done.
  3 KB (369 words) - 14:29, 25 January 2023
• High resolution, low power Sigma Delta ADC
  ...ensors and LOCs need various electronic blocks and nearly all of them need analog to digital converters (ADCs) to be able to process the data. *Analog Integrated Circuits
  2 KB (223 words) - 11:29, 14 February 2023
• Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening
  ...rify this chip in the effort to improve the throughput and efficacy of the design build test learn cycle used to develop cell strains containing desired prop *Analog Integrated Circuits
  2 KB (264 words) - 16:46, 17 February 2023
• Digital Control of a DC/DC Buck Converter
  ...oltage from 3.7V (nominal battery voltage) to 1.5V (input of the LDO). The analog part of this DC/DC has already been designed in TSMC 65nm CMOS. ...e simulated. Then, the digital controller required will be implemented and mixed signal simulations will be performed. If time allows, the synthesis of this
  2 KB (336 words) - 18:06, 1 March 2023
• Cycle-Accurate Event-Based Simulation of Snitch Core
  ...io, high-level simulators play an essential role in breaking the speed and design effort bottlenecks of cycle-accurate simulators and FPGA prototypes, respec ...show that GVSoC enables practical functional and performance analysis and design exploration at the full-platform level (processors, memory, peripherals and
  14 KB (2,018 words) - 22:54, 23 November 2023
• Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
  * Showing participation in non-curricular analog/digital projects is a plus. * Circuit design tools (e.g., Altium Designer).
  7 KB (903 words) - 10:04, 24 July 2023