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- [[Category:Processor]]4 KB (597 words) - 16:57, 12 July 2022
- [[Category:Processor]]2 KB (240 words) - 16:57, 12 July 2022
- [[Category:Processor]]2 KB (268 words) - 16:57, 12 July 2022
- ...e-core microcontrollers (i.e. Arm-Cortex-M family) or MultiCore (i.e. PULP Processor designed in IIS)4 KB (609 words) - 13:52, 12 June 2018
- ...spective users can develop their programs, and transfer them to the RISC-V processor, as well as establish connections to basic peripherals. It is planned to ma [[Category:Processor]]4 KB (497 words) - 16:50, 21 June 2018
- ...converters (ADCs) and a digital part that streams the signals to a digital processor. This part is usually implemented with standard protocols like SPI or USB. ...text of action potentials, a neural recording system can send to a digital processor only the spikes and do not send anything when the only content of the signa8 KB (1,269 words) - 18:40, 5 September 2019
- =Extremely Resilient Hyperdimensional Processor= ...project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient controller based on principles of HD computing, an17 KB (2,419 words) - 20:09, 10 March 2024
- [[Category:Processor]]5 KB (614 words) - 15:02, 4 March 2019
- ...mW 8-Channel Advanced Brain–Computer Interface Platform With a Nine-Core Processor and BLE Connectivity3 KB (437 words) - 19:03, 6 December 2023
- [[Category:Processor]]6 KB (820 words) - 12:13, 23 July 2023
- [[Category:Processor]]5 KB (644 words) - 18:18, 21 July 2023
- [[Category:Processor]]4 KB (551 words) - 11:06, 11 July 2019
- [[Category:Processor]]4 KB (517 words) - 17:09, 16 September 2021
- * compares against Ara, a vector processor based on the RISC-V Vector extension ...8] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/20186 KB (799 words) - 13:42, 10 November 2020
- [[Category:Processor]]7 KB (1,030 words) - 19:05, 29 January 2021
- ...thumb|800px|These two ''timing channel matrices'' of a Haswell class Intel processor show the conditional probability of observing an output symbol (vertical ax ...tigate how such ''hardware knobs'' can be added to the Ariane 64bit RISC-V processor and come up with a proof-of-concept implementation. Insights gained during6 KB (915 words) - 18:16, 20 May 2020
- [[Category:Processor]]5 KB (623 words) - 10:32, 5 November 2019
- [[Category:Processor]]6 KB (735 words) - 12:12, 23 July 2023
- ...Laboratory (IIS) we have been working for several years on ultra-low-power processor cores in the context of the ''PULP'' (Parallel Ultra-Low Power) project. PU In order for FP arithmetic being fast and energy-efficient in a processor core, a dedicated floating-point unit (FPU) in hardware is needed. RISC-V d8 KB (1,135 words) - 17:09, 29 July 2020
- .... The previously developed digital baseband receiver block integrated in a processor system shall be used as a starting point. As a first step you will identify3 KB (431 words) - 21:47, 18 November 2019
- [[Category:Processor]]4 KB (589 words) - 19:19, 29 January 2021
- ...le Modular Redundancy (TMR), to ensure a reliability level. For example, a processor core is replicated an odd number of times, and a voting mechanism is used t ...be used in combination with the [https://www.github.com/lowRISC/ibex Ibex] processor core. Similar to RI5CY, Ibex implements the RV32IMC instruction set archite6 KB (980 words) - 14:46, 2 June 2021
- ...d with low power consumption in mind and leveraging a the energy efficient processor. A whole working demostrator is planned to be achieved by the student. This4 KB (519 words) - 15:41, 10 November 2020
- ...rtfolio that comes from over 20 years of experience in mixed-signal neural processor design, advanced neural routing architectures, and neural algorithms. ...and master projects in the field of neuromorphic intelligence using their processor to build a whole working embedded system. The student will deal with both h5 KB (692 words) - 15:45, 10 November 2020
- ...i, <span>“Snitch: A 10 <span class="nocase">kGE</span> pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa8 KB (1,319 words) - 10:41, 6 July 2021
- ...e the backbone of big data and scientific computing. While general-purpose processor architectures such as Intel's x86 provide good performance across a wide va ...and real-world performance as communication and data exchange between the processor and accelerator become major bottlenecks.7 KB (917 words) - 17:04, 24 November 2023
- [[Category:Processor]]5 KB (584 words) - 12:09, 29 October 2020
- [1] M. Davies et al., "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning," in IEEE Micro, vol. 38, no. 1, pp. 82-99, January/F4 KB (651 words) - 19:10, 29 January 2021
- ...ery effectively, providing better energy efficiency than a general purpose processor for applications that fit its execution model. ...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or4 KB (627 words) - 14:42, 29 October 2020
- Recently, we have proposed PPAC (Parallel Processor in Associative Content-Addressable Memory) [1], a PIM architecture that is [[Category:Processor]]7 KB (882 words) - 14:33, 28 July 2021
- ...ile is handled in a single job, helped by HWPE uloop (tiny microcoded loop processor)6 KB (814 words) - 09:55, 8 March 2023
- [[Category:Processor]]5 KB (628 words) - 12:51, 17 April 2020
- [[Category:Processor]]5 KB (662 words) - 13:31, 10 May 2023
- ...classes motor-imagery and often they are not implemented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition t6 KB (815 words) - 20:02, 10 March 2024
- ...hms and kernels and hardware that can be efficiently programmed for use in processor-based systems.11 KB (1,337 words) - 10:54, 25 January 2024
- Heterogeneous systems combine a general-purpose host processor with domain-specific Programmable Many-Core Accelerators (PMCAs). Such systems are highly versatile, due to their host processor capabilities, while having high performance and energy efficiency through t5 KB (737 words) - 17:26, 2 November 2020
- ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa11 KB (1,675 words) - 15:40, 15 March 2021
- ...us Systems on Chip (HESoCs) often couple a high-performance versatile host processor, capable of handling fully-fledged operating systems running standard softw ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa11 KB (1,617 words) - 23:59, 6 February 2021
- [[Category:Processor]]4 KB (513 words) - 14:16, 24 November 2021
- ...ways of leveraging the DaCe framework to generate code for ETH’s Snitch processor system.2 KB (333 words) - 20:05, 15 February 2021
- [[Category:Processor]]3 KB (404 words) - 10:05, 9 February 2021
- ...g frequency in a modern 12nm process with IPCs expected from that class of processor [6].3 KB (474 words) - 15:50, 17 November 2021
- * Processor Design578 bytes (56 words) - 18:59, 30 October 2020
- ...mera by FBK will be deployed and characterized in conjunction with a GAP 8 processor to enable energy-proportional image recognition on embedded platforms. Depe3 KB (449 words) - 08:41, 17 February 2021
- IBM recently contributed their A2O processor core to the open-source community. The A2O is a 2-way multithreaded out-of- ...nm technology node. It was created as an application-grade, Linux-capable processor to be integrated in large SoCs primarily targeting applications like artifi3 KB (405 words) - 15:19, 9 July 2021
- ...points (AP) distributed over a large area, communicating via a centralized processor. Having access to the extreme amount of measurements at the distributed APs [[Category:Processor]]8 KB (931 words) - 17:27, 23 November 2021
- ...Accelerators (PMCAs). Such systems are highly versatile due to their host processor capabilities while having high performance and energy efficiency through th ...ores [3]. It is a 32-bit in-order RISC-V instruction set architecture(ISA) processor with four pipeline stages, extended with signal processing instructions. PU6 KB (902 words) - 19:07, 20 January 2021
- ...e higher-level tasks (like DRAM refresh) in firmware on a dedicated RISC-V processor [[[#ref-snitch|5]]] . ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa8 KB (1,214 words) - 15:18, 9 July 2021
- ...nally, it can support he ‘M’ and ‘F’ extension through a custom co-processor interface. However, currently, there is no support for domain-specific inst ...the OpenHW Group [<nowiki/>[[#ref-CV32E40P|7]]]. It is a 32-bit in-order processor with 4 pipeline stages. In contrast to Snitch, it features custom DSP instr9 KB (1,311 words) - 00:08, 13 March 2021
- [[Category:Processor]]7 KB (882 words) - 21:34, 13 July 2022
- [[Category:Processor]]8 KB (1,011 words) - 12:25, 16 November 2023
- ...complex enough and frankly just boring whereas fully-developed IPs, like a processor core, consists of tens to hundreds of thousands gates. Even our smallest co2 KB (248 words) - 20:02, 15 February 2021
- [[Category:Processor]]5 KB (653 words) - 11:08, 12 November 2020
- [[Category:Processor]]6 KB (829 words) - 11:37, 12 November 2020
- [[Category:Processor]]6 KB (748 words) - 13:57, 12 November 2020
- [[Category:Processor]]3 KB (389 words) - 01:43, 10 February 2021
- ...earch [1], we explored the opportunity of adding streaming semantic to the processor memory architecture. This was done in in-order ...imulator [3], on top of an existing model of an ARM server-grade multicore processor. The project will be comentored by researchers from Huawei's Zurich Researc7 KB (1,003 words) - 13:25, 10 August 2021
- .... Benini, <span>“<span class="nocase">Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa11 KB (1,602 words) - 15:19, 9 July 2021
- .... Benini, <span>“<span class="nocase">Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa12 KB (1,864 words) - 12:08, 29 August 2022
- ...are, exploiting a dedicated Floating-Point Unit (FPU). This means that the processor uses a circuit that was specifically designed to compute FP operations. Thi ...FP operation with a specific function that uses only integer numbers. The processor executes this function on the FP input numbers, and, after many integer ins4 KB (536 words) - 13:25, 12 August 2022
- ...i, <span>“Snitch: A 10 <span class="nocase">kGE</span> pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa13 KB (1,887 words) - 15:51, 17 November 2021
- ...ery effectively, providing better energy efficiency than a general-purpose processor for applications that fit its execution model (e.g., machine learning, and ...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or6 KB (916 words) - 15:25, 9 July 2021
- ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa8 KB (1,220 words) - 15:18, 9 July 2021
- A interesting field suitable to both domains is ''processor design'': the rising popularity and widespread adoption of the open RISC-V ...uiki, T. Hoefler, and L. Benini, <span>“Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa10 KB (1,521 words) - 15:21, 9 July 2021
- ...uiki, T. Hoefler, and L. Benini, <span>“Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloa11 KB (1,519 words) - 15:20, 9 July 2021
- ...a vector processor for full compliance of the RVV 1.0 Vector standard || Processor Design || digital VLSI design || [[:User:Mperotti | Matteo Perotti]] (ETH),6 KB (799 words) - 11:11, 1 August 2022
- ...e to implement custom co-processors and ISA extensions for existing RISC-V processor cores. Just like Ibex [1], the work for this extension interface has been s ...ng unit (VPU), or the development of a new accelerator such as a string co-processor. The project can be done in the context of a single-core or multi-core syst6 KB (835 words) - 12:52, 27 April 2021
- The goal of the mini-project is to explore a processor i.MX 7ULP from NXP) for low-power ultrasound data streaming through WiFi.2 KB (240 words) - 16:56, 16 September 2022
- ...Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa10 KB (1,434 words) - 17:20, 2 August 2021
- We can take inspiration on Ara, a RISC-V-based vector processor developed by our group. ...F. Schuiki, T. Hoefler, and L. Benini, "Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa11 KB (1,609 words) - 10:00, 30 June 2022
- ...and the BioWolf wearable ExG device, which has the PULP Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of detecting v2 KB (313 words) - 15:25, 23 October 2023
- [[Category:Processor]]6 KB (687 words) - 13:32, 10 May 2023
- [[Category:Processor]]5 KB (659 words) - 14:08, 15 February 2024
- ...ynchronous VLSI designs; right: automatically-generated layout of a simple processor implemented using ACT and fabricated in 65nm CMOS. ]] [[Category:Processor]]6 KB (725 words) - 17:36, 20 October 2021
- * Our vector processor Ara [5]3 KB (431 words) - 16:13, 6 November 2022
- Recently, we have proposed PPAC (Parallel Processor in Associative Content-Addressable Memory) [1], a PIM architecture that is [[Category:Processor]]7 KB (933 words) - 19:29, 21 November 2021
- * Processor Design931 bytes (108 words) - 10:30, 22 November 2021
- ...ps://ieeexplore.ieee.org/document/9216552 Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa4 KB (567 words) - 13:57, 7 September 2022
- ...e hardware-level, you can make sure that they can quickly propagate to the processor by moving parts that are slow such as the handshaking into hardware and pro4 KB (508 words) - 18:59, 10 January 2022
- .... Benini, <span>“<span class="nocase">Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa ...ne">S. Mazzola, <span>“<span class="nocase">ISA extensions in the Snitch Processor for Signal Processing</span>,”</span> Apr. 2021.</span>10 KB (1,428 words) - 13:31, 27 October 2022
- ...ps://ieeexplore.ieee.org/document/9216552 Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloa ...he_Snitch_Processor_for_Signal_Processing_(M) ISA extensions in the Snitch Processor for Signal Processing (M)] (Previous Master thesis project)6 KB (770 words) - 14:19, 15 September 2022
- PPAC (Parallel Processor in Associative Content-Addressable Memory) [1] is a hardware accelerator th ...benchmarking, the student will also integrate PPAC together with a RISC-V processor.7 KB (804 words) - 19:45, 21 November 2021
- In ARM based SoCs the PCS (System Control Processor, SCP) interacts with the OS via the System Control and Management Interface3 KB (467 words) - 13:55, 12 October 2022
- [[Category:Processor]]4 KB (520 words) - 14:52, 24 November 2021
- ...to compare the performance of a broad set of functions running on various processor architectures (e.g. Intel/AMD x86, ARMv8, RISC-V) in order to gain insight ...Ideally, we would also run the same set of benchmarks on an Intel/AMD x86 processor (possibly via Cloudlab), and an ARMv8 such as the ThunderX1 found in Enzian6 KB (905 words) - 21:41, 6 December 2021
- Goal of this project is to implement a Watchdog Timer (WDT) for a PULP processor core. While a preliminary specification from RISC-V is available, a few add2 KB (337 words) - 08:49, 21 June 2022
- ...and require an immensely large circuit area. Ara [1], our in-house vector Processor (RISC-V Vector Extension Version 0.10) e.g. has a complexity of multiple MG3 KB (384 words) - 12:13, 21 June 2022
- ...and the BioWolf wearable ExG device, which has the PULP Mr. Wolf multicore processor on board. The project’s goal is to design a system capable of acquiring r ...mW 8-Channel Advanced Brain–Computer Interface Platform With a Nine-Core Processor and BLE Connectivity3 KB (369 words) - 15:04, 20 July 2023
- ...ng HW has to guarantee fast propagation of the interrupt lines towards the processor, with a per-interrupt, fine-grained control over each line, and support int4 KB (515 words) - 15:06, 5 August 2022
- ...ically adjusting the operating point of a High Performance Computing (HPC) processor to meet energy, power, and thermal constraints. [3] https://www.european-processor-initiative.eu/6 KB (835 words) - 16:27, 7 July 2023
- [[Category:Processor]]4 KB (535 words) - 16:56, 12 July 2022
- ...gate level to ensure reliability, other schemes replicate entire blocks or processor cores, or only add Error Correcting Codes (ECC) to data stored in memory.2 KB (311 words) - 08:49, 21 June 2022
- ...“FUGAKU”, the most performant supercomputer in the world, is a vector processor! What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a pro4 KB (580 words) - 11:37, 3 November 2023
- [[Category:Processor]]5 KB (564 words) - 16:12, 9 February 2022
- [[Category:Processor]]5 KB (586 words) - 16:15, 9 February 2022
- ...yflie featuring both a UWB module as well as an ultra low-power multi-core processor, GAP8. Your task will include porting the driver for the array ToF sensor t3 KB (507 words) - 15:09, 11 February 2022
- [[Category:Processor]]7 KB (831 words) - 19:36, 12 January 2023
- [[Category:Processor]]6 KB (839 words) - 14:08, 15 February 2024
- The unit should take advantage of the existing PMCs in the processor, introduce new ones if needed and implement the necessary logic to monitor6 KB (869 words) - 14:47, 7 July 2023
- [[Category:Processor]]4 KB (503 words) - 13:54, 30 May 2022