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• An FPGA-Based Testbed for 3G Mobile Communications Receivers
  In this project you will develop and FPGA-based testbed for the 3G standard TD-SCDMA, with the option to extend it with an ASIC in the
  1 KB (169 words) - 16:42, 9 December 2015
• Vector Processor for In-Memory Computing
  : Interest in processor design : 40% Architecture Design & Exploration
  3 KB (443 words) - 13:10, 2 November 2015
• FFT-based Convolutional Network Accelerator
  ...The focus of this work is on speeding up this step by creating an ASIC or FPGA accelerator to perform this step faster and more power-efficiently in the f [[Category:Digital]] [[Category:FPGA]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2015]]
  8 KB (1,145 words) - 11:30, 5 February 2016
• High-speed Scene Labeling on FPGA
  ...and a display or an ethernet adapter. As opposed to an ASIC project, such FPGA and hardware-software codesign work is much more applicable in industry and [[Category:Digital]] [[Category:FPGA]] [[Category:Completed]] [[Category:2016]] [[Category:Semester Thesis]]
  8 KB (1,197 words) - 18:18, 29 August 2016
• Michael Muehlberghuber
  * Digital design, design flows, ASIC design * ASIC and FPGA design of cryptographic hardware
  1 KB (139 words) - 12:39, 7 November 2017
• Time Synchronization for 3G Mobile Communications
  ...er working with FPGAs, you can alternatively implement the algorithm on an FPGA and test it in real-time and with real data on our 3G testbed. [[Category:Digital]]
  3 KB (420 words) - 11:22, 14 April 2016
• Spatio-Temporal Video Filtering
  * '''[[Design Review]]''' ...esis]] [[Category:Hot]] [[Category:Completed]][[Category:ASIC]] [[Category:FPGA]] [[Category:2016]]
  3 KB (373 words) - 19:40, 14 April 2016
• Switched Capacitor Based Bandgap-Reference
  ...re important building blocks in analog and mixed-signal integrated circuit design. The classical Band Gap-Reference combines the negative VBE temperature coe ...is offers the possibility to study main aspects of analog and mixed-signal design, such as noise, linearity, matching, small signal-concepts and power consum
  4 KB (471 words) - 11:13, 3 May 2018
• Compressed Sensing vs JPEG
  ...le step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very li ...al ASIC (Application Specific Integrated Circuit) or the implementation in FPGA (Field-Programmable Gate Array).
  2 KB (343 words) - 10:24, 14 September 2016
• Compressed Sensing for Wireless Biosignal Monitoring
  ...le step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very li ...V4.0_Homer.html] including analog front-end, analog-to-digital conversion, digital signal processing and a compressed sensing encoder stage.
  2 KB (353 words) - 08:35, 20 January 2021
• Improving our Smart Camera System
  [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]] * for the student(s) to get to know the FPGA design flow from specification through architecture exploration to implementation,
  8 KB (1,176 words) - 16:26, 30 October 2020
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  [[File:origami-fpga-system.png|400px|thumb]] ...e Origami accelerator to run efficiently on the FPGA, hardware/software-co-design configuring memory and DMA controllers, building small IP cores to finish t
  3 KB (397 words) - 18:17, 29 August 2016
• Internet of Things Network Synchronizer
  ...he [[stoneEDGE]] project and the [[evalEDGE]] RF board. Synthesis and ASIC design are also an option. [[Category:Digital]]
  4 KB (582 words) - 20:00, 26 September 2017
• Rethinking our Convolutional Network Accelerator Architecture
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Not available]] [[Category:Semester Thesis]] [[Category:Master ...hitecture exploration to implementation, functional verification, back-end design and silicon testing.
  9 KB (1,263 words) - 18:52, 12 December 2016
• Non-binary LDPC Decoder for Deep-Space Optical Communications
  ...master project the complete decoder could be implemented and tested on an FPGA. : 30% RTL Design
  2 KB (290 words) - 16:05, 21 July 2016
• Turbo Equalization for Cellular IoT
  ...hm to an HDL implementation and synthesize it either towards an FPGA or an ASIC implementation in order to analyze the hardware complexity of the developed * '''[[Design Review]]'''
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [4] capable of implementing PULP [5] with 4 to 8 clusters and a total of 32 ...mplementation on the Xilinx Virtex-7 FPGA but if desired, an ASIC back-end design can also be implemented.
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  ...developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decode : 30% Architectural Design
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  ...developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decode : 30% Architectural Design
  3 KB (418 words) - 14:01, 13 November 2020
• Bringing XNOR-nets (ConvNets) to Silicon
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016]] ...hitecture exploration to implementation, functional verification, back-end design and silicon testing.
  10 KB (1,357 words) - 16:25, 30 October 2020

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