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  • Ultra-low power processor design
    [[File:Ultra-low power processor design.jpg|thumb]] ...use a state of the art 28nm SOI process to evaluate the performance of the processor.
    10 KB (1,669 words) - 19:01, 30 January 2014
  • SHAre - An application Specific Instruction Set Processor for SHA-2/3
    2 KB (302 words) - 12:09, 26 March 2015
  • DMA Streaming Co-processor
    ...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]] ...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.
    2 KB (344 words) - 10:30, 5 November 2019
  • ASIC Design of a Gaussian Message Passing Processor
    ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
    1 KB (210 words) - 08:34, 20 January 2021
  • ASIC Design of a Sigma Point Processor
    ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
    2 KB (265 words) - 08:34, 20 January 2021
  • Vector Processor for In-Memory Computing
    ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design
    3 KB (443 words) - 13:10, 2 November 2015
  • Digital Audio Processor for Cellular Applications
    ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
    1 KB (229 words) - 18:01, 29 March 2017
  • Baseband Processor Development for 4G IoT
    The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform
    2 KB (347 words) - 17:58, 14 April 2016
  • Design of a VLIW processor architecture based on RISC-V
    ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
    3 KB (377 words) - 10:25, 5 November 2019
  • Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
    ...d system architecture will be developed around an Ultra low power parallel processor developed at IIS to show to be ideally suited to interface
    4 KB (518 words) - 11:40, 2 February 2018
  • Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
    ...ery effectively, providing better energy efficiency than a general purpose processor for applications that fit its execution model. ...ner, Luca Benini. Ara: A 1GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22nm FD-SOI. [https://doi.or
    4 KB (627 words) - 14:42, 29 October 2020
  • Real-Time Motor-Imagery Classification Using Neuromorphic Processor
    ...classes motor-imagery and often they are not implemented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition t
    6 KB (815 words) - 20:02, 10 March 2024
  • ISA extensions in the Snitch Processor for Signal Processing (1M)
    0 bytes (0 words) - 19:24, 2 November 2020
  • ISA extensions in the Snitch Processor for Signal Processing (M)
    ...nally, it can support he ‘M’ and ‘F’ extension through a custom co-processor interface. However, currently, there is no support for domain-specific inst ...the OpenHW Group [<nowiki/>[[#ref-CV32E40P|7]]]. It is a 32-bit in-order processor with 4 pipeline stages. In contrast to Snitch, it features custom DSP instr
    9 KB (1,311 words) - 00:08, 13 March 2021
  • Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
    <!-- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) --> The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal
    5 KB (651 words) - 20:42, 22 November 2022

Page text matches

  • Ultra-low power processor design
    [[File:Ultra-low power processor design.jpg|thumb]] ...use a state of the art 28nm SOI process to evaluate the performance of the processor.
    10 KB (1,669 words) - 19:01, 30 January 2014
  • Variability Tolerant Ultra Low Power Cluster
    At the IIS we are working on an ultra low-power multi-processor (PULP) multi-processor shared-memory cluster.
    3 KB (409 words) - 10:52, 27 March 2014
  • Template
    [[Category:Processor]]
    4 KB (397 words) - 15:44, 14 February 2023
  • Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
    [[Category:Processor]]
    6 KB (741 words) - 18:14, 21 July 2023
  • Accelerators for object detection and tracking
    At the IIS we are working on an ultra low-power multi-processor processing applications that can be included in the multi-processor
    3 KB (407 words) - 10:57, 5 November 2019
  • Digital Audio High Level Synthesis for FPGAs
    #REDIRECT [[Digital Audio Processor for Cellular Applications]]
    63 bytes (7 words) - 16:36, 3 August 2015
  • CPS Software-Configurable State-Machine
    ...ry simple tasks at a very low power budget, without having to power up the processor. Together with a low power timer, the state-machine forms what we call the
    3 KB (418 words) - 11:24, 10 November 2017
  • Design and Implementation of an Approximate Floating Point Unit
    ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...referred algorithm in hardware such that it can be integrated in the multi-processor platform.
    3 KB (377 words) - 10:58, 21 February 2018
  • Putting Together What Fits Together - GrÆStl
    GrÆStl cryptographic co-processor. Bottom: Photo of the manufactured Chameleon chip, host- ...r to accelerate the computations of the cryptographic primitives. Both the processor and GrÆStl were ported onto a low-cost FPGA and finally a comparison betwe
    3 KB (434 words) - 12:01, 26 March 2015
  • Digitally-Controlled Analog Subtractive Sound Synthesis
    [[Category:Processor]]
    5 KB (597 words) - 12:56, 4 December 2021
  • MatPHY: An Open-Source Physical Layer Development Framework
    ...e physical baseband receiver that is typically implemented on the baseband processor, assisted by accelerator blocks in dedicated hardware including TPU, digita
    3 KB (360 words) - 14:14, 27 May 2015
  • Evolved EDGE Physical Layer Incremental Redundancy Architecture
    ...cessor. The decoding of the RLC blocks takes place on a PHY Digital Signal Processor (DSP) and an accelerator attached to it.
    3 KB (397 words) - 14:12, 27 May 2015
  • IcySoC
    ...n in terms of usage of hardware accelerators, heterogeneous or homogeneous processor cores and of communication or network-on-chip that has to be implemented fo
    4 KB (568 words) - 12:48, 9 February 2015
  • DMA Streaming Co-processor
    ...le:StreamingProc.png|thumb|400px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]] ...icient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.
    2 KB (344 words) - 10:30, 5 November 2019
  • Improving Scene Labeling with Hyperspectral Data
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    6 KB (941 words) - 11:29, 5 February 2016
  • A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
    An application-specific instruction-set processor (ASIP) tailored to In addition to the "pseudo-processor-controlled approach", the
    2 KB (326 words) - 12:26, 26 March 2015
  • Hardware Accelerator Integration into Embedded Linux
    :[1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Passing]
    2 KB (236 words) - 09:46, 12 October 2017
  • PULP
    * [http://asic.ethz.ch/2021/Marsellus.html Marsellus] IoT processor based on PULPopen * [http://asic.ethz.ch/2021/Kraken.html Kraken] IoT Processor with 3 accelerators based on PULPopen. Total of 9x 32bit RI5CY cores.
    10 KB (1,563 words) - 10:09, 19 August 2022
  • Indoor Positioning with Bluetooth
    [[Category:Processor]]
    3 KB (449 words) - 12:12, 4 November 2019
  • OpenRISC SoC for Sensor Applications
    ...mplementation of the OpenRisc was completed as part of a [[Ultra-low power processor design | previous semester thesis]]. We are already using this core in our ...e, during this wake up it will store the incoming message and allowing the processor to access the incoming data and react to it.
    4 KB (667 words) - 15:23, 23 December 2016
  • ASIC Design of a Gaussian Message Passing Processor
    ...is usually attached as a fixed-function-unit to a heterogeneous multicore processor. The goal of this project is to build an ASIC design of the processor architecture. You will start by optimizing the existing VHDL and Matlab mod
    1 KB (210 words) - 08:34, 20 January 2021
  • Analog
    ...sed measurements, neural stimulation etc.) as well as powerful, PULP-based processor cores. Applications are in the field of optogenetics stimulation, ExG recor ...he field of wireless communication. Our current platform with a multi-core processor system and a great RF transceiver allows us to research upcoming wireless t
    3 KB (369 words) - 18:11, 1 March 2023
  • ASIC Design of a Sigma Point Processor
    ...a dedicated processor architecture, the goal of this project is to build a processor for sigma point belief propagation. Application specific processors of this ...ng designs and start with back-end design. After the back-end, your signal processor ASIC will be fabricated in high-end 65nm CMOS technology.
    2 KB (265 words) - 08:34, 20 January 2021
  • Android reliability governor
    Dynamic Reliability Management (DRM) techniques aims at trading-off processor performance with lifetime at run-time by modulating the working temperature
    4 KB (573 words) - 17:24, 9 February 2015
  • Design of an LTE Module for the Internet of Things
    [[Category:Processor]]
    3 KB (335 words) - 14:20, 4 November 2019
  • Design and Implementation of a Convolutional Neural Network Accelerator ASIC
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    9 KB (1,289 words) - 19:45, 24 March 2015
  • Low-power Clock Generation Solutions for 65nm Technology
    operating voltage, the clock rate of such a processor will be between
    3 KB (466 words) - 19:37, 3 March 2016
  • Evaluating the RiscV Architecture
    [[Category:Processor]]
    3 KB (374 words) - 16:24, 30 October 2020
  • Hardware/software co-programming on the Parallella platform
    ...power platform similar to the Raspberry Pi. It features a dual-core ARM A9 processor running Linux, a powerful FPGA and a 16-core accelerator chip called "Epiph
    3 KB (501 words) - 14:26, 2 September 2015
  • Gomeza old project1
    # Characterization of the time/memory overhead incurred by the inter-processor communication.
    3 KB (431 words) - 18:04, 28 January 2017
  • Acceleration and Transprecision
    ...e the backbone of big data and scientific computing. While general purpose processor architectures such as Intel's x86 provide good performance across a wide va
    2 KB (275 words) - 17:05, 24 November 2023
  • Linear Solvers for Image and Video Processing Applications
    #REDIRECT [[DMA Streaming Co-processor]]
    40 bytes (4 words) - 18:10, 14 April 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance. ...n allows the programmer to share virtual address pointers between the host processor and the accelerator in a completely transparent manner, it still requires t
    5 KB (716 words) - 13:43, 29 November 2019
  • Vector Processor for In-Memory Computing
    ...his project is to develop a simple vector processor which can be used as a processor in memory (PIM) element. During the thesis you are going to study ongoing r : Interest in processor design
    3 KB (443 words) - 13:10, 2 November 2015
  • FFT-based Convolutional Network Accelerator
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    8 KB (1,145 words) - 11:30, 5 February 2016
  • High-speed Scene Labeling on FPGA
    ...the types of layer in the ConvNet, interaction between a flow controlling processor (e.g. an ARM core on a Xilinx Zynq) and the programmable logic is foreseen. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    8 KB (1,197 words) - 18:18, 29 August 2016
  • PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
    4 KB (585 words) - 17:57, 7 November 2017
  • PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
    ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
    4 KB (554 words) - 17:57, 7 November 2017
  • Digital Audio Processor for Cellular Applications
    ...rophone into the digital domain and transfers the samples to a voice codec processor. The latter filters and compresses the data. This is done on a CPU/DSP dedi In this project a hardwired voice codec processor for commonly used voice codecs in 2G/3G/4G voice communication shall be imp
    1 KB (229 words) - 18:01, 29 March 2017
  • Switched Capacitor Based Bandgap-Reference
    [[Category:Processor]]
    4 KB (471 words) - 11:13, 3 May 2018
  • Baseband Processor Development for 4G IoT
    The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform
    2 KB (347 words) - 17:58, 14 April 2016
  • An FPGA-Based Testbed for 4G/LTE Mobile Communication
    #REDIRECT [[Baseband Processor Development for 4G IoT]]
    55 bytes (7 words) - 14:46, 28 May 2015
  • Improving our Smart Camera System
    ...X1 board to get best performance transferring data from the sensor to the processor. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    8 KB (1,176 words) - 16:26, 30 October 2020
  • System Analysis and VLSI Design of NB-IoT Baseband Processing
    [[File:lteTestbed.jpg|thumb|Figure 2: LTE testbed with digital baseband and processor on an FPGA and RF-IC on the [[evaLTE]] FMC module.]]
    2 KB (245 words) - 10:39, 6 November 2017
  • Implementing Hibernation on the ARM Cortex M0
    ...ailable before the power outage, i.e., the supply voltage is dropping, the processor state can be saved only when a power outage is imminent and thus superfluou Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibe
    3 KB (390 words) - 11:59, 20 June 2016
  • Design of State Retentive Flip-Flops
    ...ation to be retained between two calls, it is not acceptable for an entire processor core idling, for example while waiting for a DMA transfer to be completed.
    2 KB (364 words) - 09:34, 25 July 2017
  • Standard Cell Compatible Memory Array Design
    ...ocks of any processing system, in fact most of the performance of a modern processor is determined by its ability to efficiently store and retrieve data. For IC
    5 KB (769 words) - 15:54, 23 May 2018
  • Intelligent Power Management Unit (iPMU)
    ...PMU should schedule the system tasks in an optimal way and wakeup the main processor if required. Naturally, the iPMU should consume as little power as possible
    2 KB (292 words) - 11:40, 2 June 2021
  • Change-based Evaluation of Convolutional Neural Networks
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    5 KB (747 words) - 18:04, 29 August 2016
  • Rethinking our Convolutional Network Accelerator Architecture
    ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
    9 KB (1,263 words) - 18:52, 12 December 2016

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