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- (M): A Flexible Peripheral System for High-Performance Systems on Chip
- ASIC
- ASIC Design Projects
- A Post-Simulation Trace-Based RISC-V GDB Debugging Server
- A Snitch-based Compute Accelerator for HERO
- Ab-initio Simulation of Strained Thermoelectric Materials
- Acceleration and Transprecision
- All-Digital In-Memory Processing
- Analog
- AnalogInt
- Analog IC Design
- Android Software Design
- Atretter
- Audio
- Audio Signal Processing
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
- Biomedical System on Chips
- Biomedical Systems on Chip
- Brunn test
- Circuits and Systems for Nanoelectrode Array Biosensors
- Completed
- Computation of Phonon Bandstructure in III-V Nanostructures
- Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
- Cryptography
- DaCe on Snitch
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
- Deep Learning Projects
- Design and Implementation of a multi-mode multi-master I2C peripheral
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
- Design study of tunneling transistors based on a core/shell nanowire structures
- Development of a fingertip blood pressure sensor
- Digital Medical Ultrasound Imaging
- EECIS
- Elliptic Curve Accelerator for zkSNARKs
- Embedded Artificial Intelligence:Systems And Applications
- Embedded Systems and autonomous UAVs
- Enabling Standalone Operation
- Enabling Standalone Operation for a Mobile Health Platform
- Energy Efficient Circuits and IoT Systems Group
- Energy Efficient SoCs
- Event-Driven Computing
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- FPGA
- Fault Tolerance
- Finite Element Simulations of Transistors for Quantum Computing
- Flexible Electronic Systems and Embedded Epidermal Devices
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
- GRAND Hardware Implementation
- HW/SW Safety and Security
- Hardware Acceleration
- Heterogeneous SoCs
- High Performance SoCs
- Hyperdimensional Computing
- IBM A2O Core
- IBM Research–Zurich
- IP-Based SoC Generation and Configuration (1-3S)
- ISA extensions in the Snitch Processor for Signal Processing (1M)
- Implementation of a 2-D model for Li-ion batteries
- Implementation of a Heterogeneous System for Image Processing on an FPGA
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM
- Integrated Devices, Electronics, And Systems
- Integrated Information Processing
- Integrated silicon photonic structures
- Integrating Hardware Accelerators into Snitch
- Investigation of the source starvation effect in III-V MOSFET
- Low-Power Time Synchronization for IoT Applications
- Low-power chip-to-chip communication network
- Low Power Embedded Systems
- Low Power Embedded Systems and Wireless Sensors Networks
- Main Page
- Marco Bertuletti
- Matteo Perotti
- Mattia
- MemPool on HERO
- Michael Rogenmoser
- Mixed-Signal Circuit Design
- Mixed Signal IC Design
- NAND Flash Open Research Platform
- Near-Memory Training of Neural Networks
- Neural Processing
- NextGenChannelDec
- Nils Wistoff
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
- Optimal System Duty Cycling
- Optimal System Duty Cycling for a Mobile Health Platform
- Palm size chip NMR
- Positioning with Wireless Signals
- Prasadar
- Predictable Execution
- Real-Time Embedded Systems
- Real-Time Optimization
- Research
- Robert Balas
- SSR combined with FREP in LLVM/Clang
- SW/HW Predictability and Security