Category:Digital
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Pages in category "Digital"
The following 200 pages are in this category, out of 617 total.
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- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- NeuroSoC RISC-V Component (M/1-2S)
- New RVV 1.0 Vector Instructions for Ara
- Next Generation Channel Decoder
- Next Generation Synchronization Signals
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Norbert Felber
- NORX - an AEAD algorithm for the CAESAR competition
- Novel Metastability Mitigation Technique
- NVDLA meets PULP
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- Object Detection and Tracking on the Edge
- On - Device Continual Learning for Seizure Detection on GAP9
- On-Board Software for PULP on a Satellite
- On-chip clock synthesizer design and porting
- On-Device Federated Continual Learning on Nano-Drone Swarms
- On-Device Learnable Embeddings for Acoustic Environments
- Online Learning of User Features (1S)
- OpenRISC SoC for Sensor Applications
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optimizing the Pipeline in our Floating Point Architectures (1S)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- OTDOA Positioning for LTE Cat-M
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- Outdoor Precision Object Tracking for Rockfall Experiments
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- Pascal Hager
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- User:Paulin
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of ITA (2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physics is looking for PULP
- Pirmin Vogel
- Power Optimization in Multipliers
- User:Prasadar
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Predict eye movement through brain activity
- Predictable Execution on GPU Caches
- PREM Intervals and Loop Tiling
- PREM on PULP
- PREM Runtime Scheduling Policies
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Probabilistic training algorithms for quantized neural networks
- Probing the limits of fake-quantised neural networks
- PULP Freertos with LLVM
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULP-Shield for Autonomous UAV
- PULPonFPGA: Hardware L2 Cache
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- PULP’s CLIC extensions for fast interrupt handling
- Putting Together What Fits Together - GrÆStl
- PVT Dynamic Adaptation in PULPv3
R
- Radiation Testing of a PULP ASIC
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- RazorEDGE: An Evolved EDGE DBB ASIC
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Implementation of Quantum State Identification using an FPGA
- Real-time Linux on RISC-V
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Real-Time Optical Flow Using Neural Networks
- Real-Time Pedestrian Detection For Privacy Enhancement
- Real-Time Stereo to Multiview Conversion
- Real-time View Synthesis using Image Domain Warping
- Realtime Gaze Tracking on Siracusa
- Reconfigurability of SHA-3 candidates
- RedCap-5G for IOT application on prototype taped-out silicon
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Resource Partitioning of Caches
- Resource Partitioning of RPC DRAM
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Rethinking our Convolutional Network Accelerator Architecture
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Running Rust on PULP
- Runtime partitioning of L1 memory in Mempool (M)
- RVfplib
S
- Sandro Belfanti
- User:Sarjmandpour
- Satellite Internet of Things
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- User:Scheremo
- SCMI Support for Power Controller Subsystem
- Securing Block Ciphers against SCA and SIFA
- Self Aware Epilepsy Monitoring
- Self-Learning Drones based on Neural Networks
- Sensor Fusion for Rockfall Sensor Node
- Serverless Benchmarks on RISC-V (M)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Shared Correlation Accelerator for an RF SoC
- Short Range Radars For Biomedical Application
- Signal to Noise Ratio Estimation for 3G standards
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Smart Agriculture System (1-2S)
- Smart e-glasses for concealed recording of EEG signals
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Smart Meters
- Smart Patch For Heath Care And Rehabilitation
- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- SmartRing
- Softmax for Transformers (M/1-2S)
- Sound-Based Vehicle Classification and Counting (1-2S)
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Spectrometry for Environmental Monitoring (1-2S/M)
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- User:Sriedel
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- Stefan Lippuner
- Stefan Mach
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M/1-2S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Structural Health Monitoring (SHM) System (1-2S/M)
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Subject specific embeddings for transfer learning in brain-computer interfaces
- User:Susman
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- System Emulation for AR and VR devices
T
- Taimir Aguacil
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- TCNs vs. LSTMs for Embedded Platforms
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Testbed Design for Self-sustainable IoT Sensors
- Thermal Control of Mobile Devices
- User:Thoriri
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Timing Channel Mitigations for RISC-V Cores
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Toward Superposition of Brain-Computer Interface Models
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards Autonomous Navigation for Nano-Blimps
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Towards global Brain-Computer Interfaces
- Towards Self Sustainable UAVs
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Towards The Integration of E-skin into Prosthetic Devices
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Equalization for Cellular IoT
U
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Ultra low power wearable ultrasound probe
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Ultra-low power processor design
- Ultra-wideband Concurrent Ranging
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound based hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound High Speed Microbubble Tracking
- Ultrasound image data recycler
- Ultrasound Low power WiFi with IMX7
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound signal processing acceleration with CUDA
- Ultrasound-EMG combined hand gesture recognition
- Using Motion Sensors to Support Indoor Localization
V
- Variability Tolerant Ultra Low Power Cluster
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Vector Processor for In-Memory Computing
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- Virtual Memory Ara
- Visualization of Neural Architecture Search Spaces
- Visualizing Functional Microbubbles using Ultrasound Imaging
- User:Vladn
- VLSI Implementation of a 5G Ciphering Accelerator
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- VLSI Implementation Polar Decoder using High Level Synthesis
