Difference between revisions of "Category:2023"
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Latest revision as of 11:24, 29 August 2023
Pages in category "2023"
The following 89 pages are in this category, out of 89 total.
A
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
- ASIC implementation of an interpolation-based wideband massive MIMO detector
- Audio Visual Speech Recognition (1S/1M)
- Audio Visual Speech Separation (1S/1M)
B
C
- Configurable Ultra Low Power LDO
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
- Creating A Boundry Scan Generator (1-3S/B/2-3G)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Cycle-Accurate Event-Based Simulation of Snitch Core
D
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Digital Control of a DC/DC Buck Converter
E
- Efficient collective communications in FlooNoC (1M)
- Enabling Efficient Systolic Execution on MemPool (M)
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Enhancing our DMA Engine with Fault Tolerance
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
F
I
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- IP-Based SoC Generation and Configuration (1-3S/B)
J
N
O
P
R
S
T
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Towards Flexible and Printable Wearables
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Transformer Deployment on Heterogeneous Many-Core Systems
