Category:Master Thesis
From iis-projects
The projects listed here are Master thesis projects. In principle a master project at IIS can take no longer than 6 months, and the student is expected to work full time on the thesis project. In some cases it is possible to make a simplified version of the project as a semester thesis, talk to the supervisor of the project to discuss this possibility.
Pages in category "Master Thesis"
The following 200 pages are in this category, out of 423 total.
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- Heroino: Design of the next CORE-V Microcontroller
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- High resolution, low power Sigma Delta ADC
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Huawei Research
- Human Intranet
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- IBM Research
- Image and Video Processing
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a NB-IoT Positioning System
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving datarate and efficiency of ultra low power wearable ultrasound
- In-ear EEG signal acquisition
- Indoor Smart Tracking of Hospital instrumentation
- Inductive Charging Circuit for Implantable Devices
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Infrared Wake Up Radio
- Integrated silicon photonic structures-Lumiphase
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Integration Of A Smart Vision System
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Internet of Things Network Synchronizer
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Redox Processes in CBRAM
- IoT Turbo Decoder
- ISA extensions in the Snitch Processor for Signal Processing (M)
L
- LAPACK/BLAS for FPGA
- Learning at the Edge with Hardware-Aware Algorithms
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Level Crossing ADC For a Many Channels Neural Recording Interface
- LightProbe
- LightProbe - CNN-Based-Image-Reconstruction
- Low Latency Brain-Machine Interfaces
- Low Power Geolocalization And Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Clock Generation Solutions for 65nm Technology
- Low-power Temperature-insensitive Timer
- LTE IoT Network Synchronization
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
M
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Machine Learning on Ultrasound Images
- Manycore System on FPGA (M/S/G)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Modeling FlooNoC in GVSoC (S/M)
- Modular Distributed Data Collection Platform
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Multi issue OoO Ariane Backend (M)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- NeuroSoC RISC-V Component (M/1-2S)
- Next Generation Channel Decoder
- Next Generation Synchronization Signals
- Noise Figure Measurement for Cryogenic System
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Novel Metastability Mitigation Technique
- NVDLA meets PULP
O
- Object Detection and Tracking on the Edge
- On - Device Continual Learning for Seizure Detection on GAP9
- On-chip clock synthesizer design and porting
- On-Device Federated Continual Learning on Nano-Drone Swarms
- On-Device Learnable Embeddings for Acoustic Environments
- Open Power-On Chip Controller Study and Integration
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- OTDOA Positioning for LTE Cat-M
- Outdoor Precision Object Tracking for Rockfall Experiments
P
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- Phase-change memory devices for emerging computing paradigms
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Physics is looking for PULP
- Precise Ultra-low-power Timer
- Predictable Execution on GPU Caches
- PREM Intervals and Loop Tiling
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Probabilistic training algorithms for quantized neural networks
- Probing the limits of fake-quantised neural networks
- Processing of 3D Micro-tomography data for Lithium Ion Batteries
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
- Putting Together What Fits Together - GrÆStl
Q
R
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-time eye movement analysis on a tablet computer
- Real-time Linux on RISC-V
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor
- Real-Time Pedestrian Detection For Privacy Enhancement
- Receiver design for the DigRF 4G high speed serial link
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Rethinking our Convolutional Network Accelerator Architecture
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Runtime partitioning of L1 memory in Mempool (M)
S
- Satellite Internet of Things
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Sensor Fusion for Rockfall Sensor Node
- Serverless Benchmarks on RISC-V (M)
- Short Range Radars For Biomedical Application
- Single-Bit-Synapse Spiking Neural System-on-Chip
- Smart e-glasses for concealed recording of EEG signals
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Smart Patch For Heath Care And Rehabilitation
- Smart Virtual Memory Sharing
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- SmartRing
- Softmax for Transformers (M/1-2S)
- Spatio-Temporal Video Filtering
- Spiking Neural Network for Autonomous Navigation
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Standard Cell Compatible Memory Array Design
- State-Saving @ NXP
- Streaming Integer Extensions for Snitch (M/1-2S)
- Streaming Layer Normalization in ITA (M/1-2S)
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub-Noise Floor Channel Tracking
- Switched Capacitor Based Bandgap-Reference
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- System Analysis and VLSI Design of NB-IoT Baseband Processing
- System Emulation for AR and VR devices
T
- Taping a Safer Silicon Implementation of Snitch (M/2-3S)
- TCNs vs. LSTMs for Embedded Platforms
- Ternary Neural Networks for Face Recognition
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Testbed Design for Self-sustainable IoT Sensors
- Thermal Control of Mobile Devices
- Time Gain Compensation for Ultrasound Imaging
- Time Synchronization for 3G Mobile Communications
- Timing Channel Mitigations for RISC-V Cores
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- Towards Flexible and Printable Wearables
- Towards global Brain-Computer Interfaces
- Towards Self Sustainable UAVs
- Towards The Integration of E-skin into Prosthetic Devices
- Trace Debugger for custom RISC-V Core
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Turbo Equalization for Cellular IoT
U
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Ultra low power wearable ultrasound probe
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Ultra-low power sampling front-end for acquisition of physiological signals
- Ultra-low power transceiver for implantable devices
- Ultra-wideband Concurrent Ranging
- Ultrasound based hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound image data recycler
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- Ultrasound-EMG combined hand gesture recognition
- Using Motion Sensors to Support Indoor Localization
V
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Vector Processor for In-Memory Computing
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
- Virtual Memory Ara
- Visualizing Functional Microbubbles using Ultrasound Imaging
- VLSI Implementation of a 5G Ciphering Accelerator
- VLSI Implementation Polar Decoder using High Level Synthesis