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Showing below up to 250 results in range #251 to #500.
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- Energy Efficient Serial Link
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Energy Efficient SoCs
- Engineering For Kids
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- Enhancing our DMA Engine with Fault Tolerance
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Evaluating An Ultra low Power Vision Node
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating the RiscV Architecture
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Event-based navigation on autonomous nano-drones
- Every individual on the planet should have a real chance to obtain personalized medical therapy
- Evolved EDGE Physical Layer Incremental Redundancy Architecture
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring NAS spaces with C-BRED
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- FFT-based Convolutional Network Accelerator
- FFT HDL Code Generator for Multi-Antenna mmWave Communication
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
- FPGA mapping of RPC DRAM
- Fast Accelerator Context Switch for PULP
- Fast Simulation of Manycore Systems (1S)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Finite Element Simulations of Transistors for Quantum Computing
- Finite element modeling of electrochemical random access memory
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Flexible Front-End Circuit for Biomedical Data Acquisition
- Floating-Point Divide & Square Root Unit for Transprecision
- Forward error-correction ASIC using GRAND
- Freedom from Interference in Heterogeneous COTS SoCs
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- GPT on the edge
- GRAND Hardware Implementation
- GSM Voice Capacity Evolution - VAMOS
- GUI-developement for an action-cam-based eye tracking device
- Glitches Reduce Listening Time of Your iPod
- Gomeza old project1
- Gomeza old project2
- Gomeza old project3
- Gomeza old project4
- Gomeza old project5
- Graph neural networks for epileptic seizure detection
- HERO: TLB Invalidation
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Hardware Accelerated Derivative Pricing
- Hardware Acceleration
- Hardware Accelerator Integration into Embedded Linux
- Hardware Accelerator for Model Predictive Controller
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Herschmi
- High-Resolution, Calibrated Folding ADCs
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- High-speed Scene Labeling on FPGA
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High Performance Cellular Receivers in Very Advanced CMOS
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High performance continous-time Delta-Sigma ADC for biomedical applications
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hypervisor Extension for Ariane (M)
- IBM A2O Core
- IBM Research–Zurich
- IP-Based SoC Generation and Configuration (1-3S)
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (1M)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Image Sensor Interface and Pre-processing
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Implementation of a 2-D model for Li-ion batteries
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving Resiliency of Hyperdimensional Computing
- Improving Scene Labeling with Hyperspectral Data
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- Improving datarate and efficiency of ultra low power wearable ultrasound
- Improving our Smart Camera System
- In-ear EEG signal acquisition
- Indoor Positioning with Bluetooth
- Indoor Smart Tracking of Hospital instrumentation
- Inductive Charging Circuit for Implantable Devices
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
- Infrared Wake Up Radio
- Integrated silicon photonic structures
- Integrated silicon photonic structures-Lumiphase
- Integrating Hardware Accelerators into Snitch
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Integration Of A Smart Vision System
- Intelligent Power Management Unit (iPMU)
- Interference Cancellation for EC-GSM-IoT
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
- Interference Cancellation for the cellular Internet of Things
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Investigation of the source starvation effect in III-V MOSFET
- IoT Turbo Decoder
- Jammer-Resilient Synchronization for Wireless Communications
- Jammer Mitigation Meets Machine Learning
- Kinetic Energy Harvesting For Autonomous Smart Watches
- Knowledge Distillation for Embedded Machine Learning
- LAPACK/BLAS for FPGA
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology
- LTE IoT Network Synchronization
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Learning at the Edge with Hardware-Aware Algorithms
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Libria
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - CNN-Based-Image-Reconstruction
- LightProbe - Design of a High-Speed Optical Link
- LightProbe - Frontend Firmware and Control Side Channel
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - Thermal-Power aware on-head Beamforming
- LightProbe - Ultracompact Power Supply PCB
- LightProbe - WIFI extension (PCB)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
- Linux Driver for fine-grain and low overhead access to on-chip performance counters
- Low-Complexity MIMO Detection
- Low-Dropout Regulators for Magnetic Resonance Imaging
- Low-Power Time Synchronization for IoT Applications
- Low-Resolution 5G Beamforming Codebook Design
- Low-power Clock Generation Solutions for 65nm Technology
- Low-power Temperature-insensitive Timer
- Low-power chip-to-chip communication network
- Low-power time synchronization for IoT applications
- Low Latency Brain-Machine Interfaces
- Low Power Embedded Systems and Wireless Sensors Networks
- Low Power Geolocalization And Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Precision Ara for ML
- Low Resolution Neural Networks
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Machine Learning on Ultrasound Images
- Main Page
- Make Cellular Internet of Things Receivers Smart
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Matheus Cavalcante
- Mattia
- MemPool on HERO
- MemPool on HERO (1S)
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- Minimal Cost RISC-V core
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- Modeling FlooNoC in GVSoC (S/M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Modular Distributed Data Collection Platform
- Modular Frequency-Modulation (FM) Music Synthesizer
- Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Moritz Schneider
- Multi-Band Receiver Design for LTE Mobile Communication
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
- NAND Flash Open Research Platform
- NORX - an AEAD algorithm for the CAESAR competition
- NVDLA meets PULP
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
- Near-Memory Training of Neural Networks
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neural Processing
- Neural Recording Interface and Signal Processing
- Neural Recording Interface and Spike Sorting Algorithm
- NeuroSoC RISC-V Component (M/1-2S)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- NextGenChannelDec
- Next Generation Synchronization Signals
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Novel Metastability Mitigation Technique
- Novel Methods for Jammer Mitigation
- Object Detection and Tracking on the Edge
- On-Board Software for PULP on a Satellite
