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- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1 Semester/Bachelor students6 KB (741 words) - 18:14, 21 July 2023
- <!-- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) -->1 KB (188 words) - 09:39, 3 November 2023
- : Looking for 1-2 Semester/Master students6 KB (820 words) - 12:13, 23 July 2023
- : Looking for 1 Semester/Bachelor students5 KB (644 words) - 18:18, 21 July 2023
- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1-2 Semester/Master students6 KB (735 words) - 12:12, 23 July 2023
- #Redirect [[A Snitch-based Compute Accelerator for HERO (M/1-2S)]]66 bytes (10 words) - 21:47, 10 November 2020
- <!-- (M/1-2S): A Snitch-based Compute Accelerator for HERO --> ...pen-source Parallel Ultra-Low Power (PULP) platform [<nowiki/>[[#ref-pulp|1]]] , which provides a multicore cluster based on the open RISC-V instructio11 KB (1,617 words) - 23:59, 6 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]2 KB (333 words) - 20:05, 15 February 2021
- #Redirect [[LLVM and DaCe for Snitch (1-2S)]] ...ttps://scholar.google.com/scholar?oi=bibs&cluster=8341123140790442037&btnI=1&hl=de Snitch]3 KB (386 words) - 20:06, 15 February 2021
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- 1. Install MemPool and test it on different configurations ...RTL language (SystemVerilog or Verilog or VHDL). Having followed the VLSI 1 course is recommended.8 KB (1,196 words) - 10:41, 6 July 2021
- <!-- (1-2S): An RPC DRAM Implementation for Energy-Efficient ASICs --> .... These ''reduced pin count DDR'' (RPC DDR) [[[#ref-rpc_dram_website|1]]] memories only require a simple on-chip PHY and can operate with regular8 KB (1,214 words) - 15:18, 9 July 2021
- #Redirect [[A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)]]2 KB (365 words) - 20:03, 15 February 2021
- ...Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) --> ...Ariane cores, and die-to-die serial link. [[#ref-zaruba2020manticore|[1]]]]]11 KB (1,602 words) - 15:19, 9 July 2021
- Ara is working well, with a prototype achieving an operating frequency of 1 GHz in a modern technology. 1. Familiarize with the RISC-V Vector Extension and the Ara source code. (~26 KB (916 words) - 15:25, 9 July 2021
- <!-- (1-2S/B): A Snitch-Based SoC on iCE40 FPGAs --> With the iCE40 FPGA family, Lattice Semiconductor [[[#ref-fpga|1]]] provides FPGAs with the world’s smallest form factor, optimized for u8 KB (1,220 words) - 15:18, 9 July 2021
- <!-- LLVM and DaCe for Snitch (1-2S) --> The Snitch ecosystem [[#ref-zaruba2020snitch|[1]]] targets energy-efficient high-performance systems. It is built aroun11 KB (1,519 words) - 15:20, 9 July 2021
- <!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> ...ts following predefined address patterns. Recent architectural extensions [1-5] propose handling such streams in hardware. This frees processors from ex4 KB (557 words) - 16:14, 6 November 2022
- <!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> ...s following a predefined address pattern. Recent architectural extensions [1,2] propose handling such streams in hardware, which brings many benefits: i3 KB (431 words) - 16:13, 6 November 2022
- <!-- Counter-based Fast Power Estimation using FPGAs (M/1-3S) --> ...ly approximated by randomly selecting a handful of signals to be observed [1].5 KB (688 words) - 13:51, 27 October 2022
- #REDIRECT [[Adding Linux Support to our DMA Engine (1-2S/B)]]61 bytes (11 words) - 17:27, 19 November 2021
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2 KB (244 words) - 12:12, 21 June 2022
- The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the [1] https://ieeexplore.ieee.org/document/92165524 KB (554 words) - 09:49, 17 August 2022
- <!-- Streaming Integer Extensions for Snitch (M/1-2S) --> The Snitch ecosystem [1] targets energy-efficient high-performance systems. It is built around the6 KB (770 words) - 14:19, 15 September 2022
- <!-- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) --> ...r processors are complex and require an immensely large circuit area. Ara [1], our in-house vector Processor (RISC-V Vector Extension Version 0.10) e.g.3 KB (384 words) - 12:13, 21 June 2022
- <!-- Creating Extension and Evaluation of TinyDMA (1-2S/B/2-3G) --> Currently, TinyDMA is based on the AMBA AXI4[1] on-chip communication standard. Next to AXI4, simpler protocols are used t2 KB (312 words) - 09:35, 3 November 2023
- ...ng Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) -->2 KB (282 words) - 09:27, 3 November 2023
- ...ng a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) -->2 KB (226 words) - 14:22, 27 February 2024
- <!-- Creating Towards Formal Verification of the iDMA Engine (1-3S/B) -->2 KB (272 words) - 10:21, 3 November 2023
- <!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) -->2 KB (214 words) - 09:39, 23 August 2023
- <!-- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) --> ...arrays in fixed, possibly irregular patterns relative to each grid point [1]. They are widespread in high-performance computing (HPC) and underly vario3 KB (431 words) - 22:29, 19 January 2023
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- ...eating Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) -->3 KB (392 words) - 09:38, 3 November 2023
- .../asic.ethz.ch/2022/Neo.html Neo], feature a Linux-capable '''CVA6''' core [1] and a '''Serial Link''' off-chip interface. While the chips contain a few * [1] https://github.com/openhwgroup/cva63 KB (416 words) - 10:49, 25 January 2024
- ...the concept Manticore architecture that went on display at HotChips 2020 [1]. It couples a 64-bit RISC-V application-class out-of-order CVA6 core [2,3] [1] [https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9296802 Manticor7 KB (944 words) - 10:47, 25 January 2024
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- ...pendent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) -->2 KB (335 words) - 13:58, 27 October 2022
- <!-- All the flavours of FFT on MemPool (1-2S/B) --> MemPool [[#ref-Cavalcante2020|[1]]] is a IIS-born many-core system, having 256 Snitch cores and 1024 ban3 KB (460 words) - 18:54, 9 November 2022
- ...ing A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> ...effort. A simple solution to this problem was introduced in 1996 with USB 1.0.2 KB (220 words) - 09:27, 3 November 2023
- ...s a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) -->2 KB (290 words) - 09:38, 3 November 2023
- ...ndent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) -->2 KB (223 words) - 17:18, 18 December 2023
- ...ng a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) -->2 KB (250 words) - 09:31, 29 August 2023
- <!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) -->2 KB (249 words) - 09:36, 3 November 2023
- <!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --> TileLink (https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) is a chip-scale interconnect standard providing multiple maste1 KB (181 words) - 09:36, 3 November 2023
- <!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) -->2 KB (297 words) - 09:36, 3 November 2023
- ...Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) --> ...heavily present in communications kernels. The Spatz [[#ref-Spatz2022|[1]]], a small and energy-efficient vector unit based on the RISC-V vector6 KB (775 words) - 11:57, 31 October 2023
- ...ely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally stores a copy of recently accessed memory cont * [1] https://github.com/openhwgroup/cva62 KB (260 words) - 16:41, 15 November 2022
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- <!-- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) --> [[File:occamy_block_diagram.png|thumb|Figure 1: A block diagram of the Occamy chip architecture]]8 KB (1,177 words) - 11:45, 13 March 2024
- : Looking for 1-2 Semester/Master students6 KB (688 words) - 12:15, 23 July 2023
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- : Looking for 1-2 Bachelor or Semester students / 1 Master student6 KB (735 words) - 12:15, 23 July 2023
- : Looking for 1 Bachelor or Semester student5 KB (631 words) - 12:43, 23 July 2023
- : Looking for 1 Bachelor or Semester student5 KB (631 words) - 10:07, 24 July 2023
- <!-- Softmax for Transformers (M/1-2S) --> Transformers [1], initially popularized in Natural Language Processing (NLP), have found ap4 KB (573 words) - 14:46, 23 October 2023
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- <!-- Creating A Boundry Scan Generator (1-3S/B/2-3G) -->1 KB (203 words) - 09:55, 3 November 2023
- ...t, the goal is to modify a simple embedded RISC-V processor, such as Ibex [1]. The Ibex core supports both the riscv32i and the riscv32e base instructio * [1] https://github.com/lowRISC/ibex2 KB (259 words) - 11:55, 18 December 2023
- <!-- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) --> ...al family of lightweight yet high-performance data movement engines (iDMA)[1].1 KB (192 words) - 14:24, 27 February 2024
- <!-- Backend explorations for Network-on-Chips (1-2S/M) --> ...research group we implemented our own Network-on-Chip called ''FlooNoC'' [1][2], which was designed with awareness of those physical implementation eff3 KB (511 words) - 16:23, 31 October 2023
- <!-- Streaming Layer Normalization in ITA (M/1-2S) --> Transformers [1], initially popularized in Natural Language Processing (NLP), have found ap4 KB (511 words) - 12:38, 21 December 2023
- <!-- NeuroSoC RISC-V Component (M/1-2S) --> The NeuroSoC project [1] will design and demonstrate an advanced Multiprocessor System-on-Chip base3 KB (482 words) - 17:26, 10 January 2024
- ...hysical Design: Reinforcement Learning for Macro Placement and Mix-Placer (1-2S/M) --> * [1] https://dl.acm.org/doi/pdf/10.1145/3569052.35789264 KB (530 words) - 10:50, 3 November 2023
- ...tor-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M) --> ...heavily present in communications kernels. The Spatz [[#ref-Spatz2022|[1]]], a small and energy-efficient vector unit based on the RISC-V vector6 KB (844 words) - 11:41, 31 October 2023
- ...SC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) -->3 KB (342 words) - 13:02, 12 February 2024
- ...also add other enhancements. I3C specification developed by MIPI Alliance [1] , is an intelligent multi-featured interface that improves upon the key at ...e Specification for I3C® (Improved Inter Integrated Circuit), version 1.1.1, MIPI Alliance, Inc., 11 June 2021.5 KB (775 words) - 17:17, 18 December 2023
- ...ing an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) --> ...are developing a scalable and flexible family of DMA engines, called iDMA [1]. iDMA is the cluster-level DMA in both the Snitch and PULP clusters. When2 KB (314 words) - 10:27, 3 November 2023
- ...sical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)]]106 bytes (14 words) - 10:50, 3 November 2023
- ...ed Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) --> [1] “A High-performance, Energy-efficient Modular DMA Engine Architecture”2 KB (332 words) - 11:18, 3 November 2023
- <!-- Implementation of an Accelerator for Retentive Networks (M/1-2S) --> ...ars, a new class of deep learning algorithm, the Transformer architecture [1], has emerged.5 KB (735 words) - 14:31, 18 February 2024
- <!-- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) -->1 KB (165 words) - 17:19, 13 November 2023
- <!-- Writing a Hero runtime for EPAC (1-3S/B) --> #pragma omp target device(1)4 KB (501 words) - 15:27, 15 February 2024
- ...HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) -->3 KB (461 words) - 12:19, 12 February 2024
- ...HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) --> MemPool[1] is an example of the massively parallel SoCs built at IIS. It integrates 23 KB (482 words) - 15:57, 13 February 2024
- Within the WP3 of the UrbanTwin Project [1], we have designed and produced a compact, low-power, highly efficient comp [1] [https://urbantwin.ch/ Urban Twin Project]4 KB (568 words) - 13:26, 10 May 2024
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Page text matches
- * Consider about 1 slide per minute on average for your slides.1 KB (187 words) - 18:53, 22 March 2020
- : Looking for 1-2 Semester/Master students3 KB (409 words) - 10:52, 27 March 2014
- : Looking for 1-2 Semester/Master students4 KB (397 words) - 15:44, 14 February 2023
- ...ion methods including magnetic, electrostatic, and electrochemical effects[1,2,3], thus they can be better controlled for many applications. To better u2 KB (328 words) - 10:21, 14 February 2023
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''4 KB (444 words) - 12:43, 23 July 2023
- ...lled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)]]112 bytes (13 words) - 08:11, 8 February 2023
- : Looking for 1 Semester/Bachelor students6 KB (741 words) - 18:14, 21 July 2023
- ...bi equalizer. A high-level block diagram of the algorithm is shown in Fig. 1. In the ing is explained in more details in [1]. The preprocessing step is concluded with deciding over5 KB (684 words) - 10:43, 6 November 2017
- * Start with a 1-2 sentence summary of your project. (this can be repeated every week the sa IPC = 1).7 KB (1,133 words) - 07:08, 7 October 2023
- ...correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transcei : Looking for 1-2 Semester/Master students3 KB (382 words) - 20:00, 26 September 2017
- <!--: Looking for 1-2 Semester/Master students3 KB (392 words) - 12:33, 15 April 2016
- : Looking for 1-2 Semester/Master students3 KB (385 words) - 11:13, 14 April 2016
- : Looking for 1-2 Semester/Master students3 KB (508 words) - 11:12, 14 April 2016
- : Looking for 1-2 Semester/Master students2 KB (300 words) - 14:11, 13 March 2014
- : Looking for 1-2 Semester/Master students3 KB (492 words) - 12:34, 7 November 2017
- : Looking for 1-2 Semester/Master students3 KB (407 words) - 10:57, 5 November 2019
- : Looking for 1 Master student3 KB (429 words) - 09:42, 12 October 2017
- the OsmocomBB project [1] has implemented a relatively [1] OsmocomBB. http://bb.osmocom.org/trac/, April 2015.3 KB (421 words) - 10:40, 6 November 2017
- ...aseband Processing (DBB) from the [[RazorEDGE]] project on an ML605 board [1] and RF processing on the [[evalEDGE]] FMC module is available. A separate [1] [http://www.xilinx.com/ml605 Virtex-6 FPGA ML605 Evaluation Kit], June 2012 KB (273 words) - 11:30, 24 February 2017
- ...the 3GPP standard organization include enhancements to 2G and 4G networks [1] refereed to as EC-GSM-IoT and NB-IoT to enhance coverage by up to 20 dB an2 KB (277 words) - 17:59, 29 March 2017
- : Looking for 1-2 Semester/Master students2 KB (329 words) - 17:44, 21 December 2017
- : Looking for 1-2 Semester/Master students2 KB (319 words) - 17:43, 21 December 2017
- : Looking for 1-2 Semester/Master students3 KB (355 words) - 12:07, 17 January 2014
- : Looking for 1-2 Master students3 KB (472 words) - 12:12, 17 January 2014
- : Looking for 1-2 Master students3 KB (389 words) - 12:28, 17 January 2014
- ...operly engineered so that high storage capacities are obtained. Based on a 1-D battery simulator that we have recently implemented, the goal of this pro : Looking for 1 Semester/Master students3 KB (362 words) - 15:43, 4 September 2019
- : Looking for 1 Master student3 KB (456 words) - 15:43, 4 September 2019
- Standard 1-D simulation models, as popularized in the mid 90's, are computationally ve : Looking for 1 Semester/Master students3 KB (431 words) - 15:41, 4 September 2019
- ...Es and is capable of computing an AES encryption and decryption in 742 and 1,025 clock cycles, respectively. Hashing of a 512-bit message according to G3 KB (434 words) - 12:01, 26 March 2015
- : Looking for 1-2 Semester/Master students3 KB (357 words) - 18:53, 6 December 2014
- ...f-merit (FoM) is 2.8 pJ/conversion while peak INL and DNL are 2.34 LSB and 1.56 LSB, respectively.2 KB (328 words) - 18:02, 29 January 2014
- ...interest. This offset voltage can exceed the signal amplitude (100 μV ...1 mV) by three orders of magnitude and is varying over time since it is affec2 KB (311 words) - 10:53, 10 March 2015
- ...s became accessible and affordable as companies, e.g. Sound Semiconductor [1] or Coolaudio [2], manufacture specialized analog integrated circuits (ICs) ...ctive synthesizer using off-the-shelf components from Sound Semiconductor [1]. The synthesizer should include one or multiple oscillators, a voltage-con5 KB (597 words) - 12:56, 4 December 2021
- : KTI 11376.1 ...[http://dx.doi.org/10.1007/s11265-014-0949-1 DOI: 10.1007/s11265-014-0949-1]3 KB (397 words) - 14:12, 27 May 2015
- ...l hundred or thousand bits, and varying code rates ranging from 0.33 up to 1. Transmission modes with very high code rates have been proved crucial for2 KB (316 words) - 10:45, 9 February 2015
- ...nce on Communication, Control, and Computing'', Monticello, Illinois, USA, 1-5 Oct 20123 KB (352 words) - 13:56, 9 February 2015
- : Looking for 1-2 Semester / Master Thesis Students2 KB (342 words) - 16:46, 11 February 2015
- : Looking for 1/2 Semester/Master students4 KB (613 words) - 19:54, 9 February 2015
- complexity IoT devices in release 12 [1]. The low complexity is achieved by single receive antenna and 1.4 MHz bandwidth2 KB (222 words) - 10:40, 6 November 2017
- : Looking for 1-2 Interested Students2 KB (344 words) - 10:30, 5 November 2019
- : Looking for 1-2 Interested Students3 KB (366 words) - 12:40, 1 June 2017
- : Looking for 1-2 Interested Students3 KB (373 words) - 11:51, 19 August 2017
- : Looking for 1-2 Semester/Master students2 KB (225 words) - 14:58, 8 March 2014
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- : Looking for 1-2 Semester students2 KB (307 words) - 20:06, 17 February 2015
- : Looking for 1-2 Semester/Master students2 KB (251 words) - 20:06, 17 February 2015
- ...ed by the IBM TrueNorth architecture [Merolla14], an homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification ...2013 International Joint Conference on Neural Networks (IJCNN), 2013, pp. 1–10.5 KB (784 words) - 14:50, 30 November 2016
- : Looking for 1-2 Semester/Master students2 KB (278 words) - 16:57, 12 July 2022
- : Looking for 1 Semester/Master student3 KB (331 words) - 15:40, 4 September 2019
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- : Looking for 1 Semester/Master student3 KB (357 words) - 15:38, 4 September 2019
- : Looking for 1 Semester student3 KB (363 words) - 15:37, 4 September 2019
- : Looking for 1 Semester/Master student3 KB (449 words) - 15:37, 4 September 2019
- : Looking for 1 Master student4 KB (488 words) - 17:12, 16 September 2021
- : Looking for 1 Master student3 KB (448 words) - 17:11, 16 September 2021
- : Looking for 1 Master student2 KB (284 words) - 17:10, 16 September 2021
- : Looking for 1 Master/ industrial internship student4 KB (608 words) - 13:58, 23 June 2021
- : Looking for 1-2 Semester students4 KB (518 words) - 16:07, 6 May 2019
- : Looking for 1-2 Semester/Master students2 KB (188 words) - 10:58, 27 March 2014
- : Looking for 1-2 Semester/Master students2 KB (348 words) - 20:01, 26 September 2017
- ...Passing algorithms in an efficient way has been developed at IIS recently [1]. :[1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Pa2 KB (236 words) - 09:46, 12 October 2017
- ...further development from GAP based on PULPopen. Total of 10x 32bit cores, 1 fabric controller + 9 in the cluster. ...//asic.ethz.ch/2017/Mr.Wolf.html Mr. Wolf] new generation PULP system with 1 fabric controller (micro-riscy) and a cluster with eight RI5CY (RISC-V core10 KB (1,563 words) - 10:09, 19 August 2022
- : Looking for 1-2 Master/Semester student3 KB (449 words) - 12:12, 4 November 2019
- ...e information of these repetitions, even though they contain changed data [1]. : Looking for 1-2 Semester/Master students3 KB (345 words) - 10:52, 5 April 2022
- : Looking for 1-2 Semester/Master students4 KB (667 words) - 15:23, 23 December 2016
- ...ature. This leads to significant higher FLOPS and smother thermal profile [1]. : Looking for 1-2 Semester/Master students3 KB (456 words) - 08:35, 20 January 2021
- LTE synchronization consists of 4 parts [1-5]: ...s Communications and Networking Conference'', 2009. WCNC 2009. IEEE, pages 1–6, April 2009.2 KB (350 words) - 17:56, 14 April 2016
- ...ended normal operation modes: NORX32-4-1, NORX32-6-1, NORX64-4-1, NORX64-6-13 KB (423 words) - 11:13, 13 June 2014
- ...used to build a processor architecture to efficiently run such algorithms [1]. A specific processor of this type is usually attached as a fixed-function [1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Pa1 KB (210 words) - 08:34, 20 January 2021
- : Looking for 1-2 Semester students3 KB (413 words) - 16:05, 21 July 2016
- Sigma point belief propagation [1] lets one describe these algorithms in a common way. While in a recent mast [1] [http://automatica.dei.unipd.it/tl_files/utenti/lucaschenato/Classes/PSC102 KB (265 words) - 08:34, 20 January 2021
- : Looking for 1 or 2 Master/Semester thesis students3 KB (378 words) - 19:56, 9 February 2015
- : Looking for 1 Master or 2 semester project students : if interested in FPGA development, VLSI 1 is required3 KB (408 words) - 13:17, 5 February 2016
- ...The latest packet switched GSM enhancement called Evolved EDGE even allows 1 Mobile Station (MS) to use 2 frequency carriers in the downlink. This furth2 KB (250 words) - 17:45, 14 April 2016
- ...increase and low-power features is likely to be introduced in March 2016 [1]. ...plexity and low throughput Internet of Things (CIoT)'', 3GPP TR 45.820 v13.1.0, 2015.3 KB (384 words) - 16:41, 17 July 2016
- ...hine (M2M) communications and the Internet of things (IoT) was introduced [1]. [1] http://www.nextgcom.co.uk/wordpress/wp-content/uploads/2014/09/ARM-NextG-L3 KB (335 words) - 14:20, 4 November 2019
- : Looking for 1 semester student2 KB (344 words) - 15:34, 4 September 2019
- : VLSI 1 and enrolment in VLSI 2 is required * Literature survey, building a basic understanding of the problem at hand (1 week)9 KB (1,289 words) - 19:45, 24 March 2015
- : Looking for 1-2 Master students3 KB (466 words) - 19:37, 3 March 2016
- : Looking for 1-2 Master students : Student 1, Student 23 KB (480 words) - 19:08, 28 January 2017
- : Looking for 1-2 Master students3 KB (438 words) - 18:06, 3 February 2015
- : Looking for 1-2 Semester/Master students2 KB (247 words) - 17:38, 21 December 2017
- ...needs to be transmitted to the following baseband ASIC can reach orders of 1 Gb/s. To avoid any disturbances to the vulnerable receiver and to mimize th : Looking for 1-2 Semester/Master students1 KB (197 words) - 17:37, 21 December 2017
- : Student 1, Student 23 KB (431 words) - 18:04, 28 January 2017
- ...d a battery. The node should also be able to have a lifetime that at least 1 days processing data and generate a pulse when particular events are detect4 KB (589 words) - 10:14, 3 August 2018
- : Looking for 1 Semester/Master student : Student 1, Student 23 KB (376 words) - 18:04, 28 January 2017
- ...or more possible ''project types'' (M/S/B/G) and a ''number of students'' (1 to 3). ...eks'' half-time (1 semester lecture period) or ''7 weeks'' full-time for ''1-3 students''7 KB (816 words) - 11:57, 8 May 2024
- ...types, while still preserving functional and timing accuracy. [1][2] 1. '''Research:''' Getting familiar with the implementation of GVSoC and how4 KB (520 words) - 15:15, 4 December 2023
- in what's called the the Internet of things (IoT) [1,2]. To realize this vision, cellular standards ...0) for Machine to Machine (M2M) communications and the IoT was introduced [1]. Since Cat-0 devices target the low-complexity M2M market, 75 percent4 KB (561 words) - 10:43, 6 November 2017
- System-in-a-Package (SiP) modems such as [1] are evalEDGE v.1.0 board. The ZedBoard can be used for controlling or7 KB (1,105 words) - 20:02, 26 September 2017
- : Looking for 1 Master or (2 or 1) semester project students (work load will be adjusted)5 KB (707 words) - 11:22, 5 February 2016
- A huge variety of integrated audio modules such as [1] exist on the marked. In cellular devices an audio chip can be placed betwe [1] [http://www.analog.com/en/audiovideo-products/audio-signal-processors/adau2 KB (286 words) - 18:15, 17 December 2015
- At IIS, we use an evaluation platform based on the Xilinx Zynq-7000 SoC [1] with PULPonFPGA [2] implemented in the programmable logic to study the int5 KB (716 words) - 13:43, 29 November 2019
- <!--: Looking for 1-2 Semester students2 KB (300 words) - 11:23, 14 April 2016
- * VLSI 1 * Fixed-point model, implementation loss, test environment (1-2 weeks)8 KB (1,145 words) - 11:30, 5 February 2016
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- .../3G/4G voice communication shall be implemented on an ASIC. Previous work [1] can be used as reference. An ASIC solution as opposed to a CPU/DSP solutio1 KB (229 words) - 18:01, 29 March 2017
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- ...ure (PTAT) current to result in a temperature independent voltage of about 1.2V. Such a voltage is not compliant with modern CMOS processes that have su ...ild a summing network for the generation of the constant band-gap voltage [1]. Switched capacitor networks have the advantage that they can be made to h4 KB (471 words) - 11:13, 3 May 2018