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• Ultra-low power processor design
  ...er, there is a lot of functionality which will never be used in the target system and it is therefore not necessary to maintain all this functionality. Remov ...of sensor and letting the processor process the sensed data, or running a software on the processor which controls a FPGA board or some other chip through the
  10 KB (1,669 words) - 19:01, 30 January 2014
• Template
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (397 words) - 15:44, 14 February 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  ...ure in such a way that later studies will allow '''ML-based control of the system'''. ...architecture is to be designed in such a way that ML-based control of the system is possible.
  6 KB (741 words) - 18:14, 21 July 2023
• Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
  the student will combine the IIS PHY with OsmocomBB software to build The IIS 2G testbed has no operating system (OS) running on
  3 KB (421 words) - 10:40, 6 November 2017
• CPS Software-Configurable State-Machine
  ...data over a wireless link. Some of these system even include an actuation system, which reacts depending on the captured data. ...nnected and operate and act collaboratively it is called a 'cyper-physical system' (CPS).
  3 KB (418 words) - 11:24, 10 November 2017
• Wireless Biomedical Signal Acquisition Device
  ...less link, e.g., to a PC or tablet running a visualization or data capture software. Although the wireless and battery-powered nature of this system reduces the impact of mains interference, its amplitude might nonetheless b
  2 KB (280 words) - 10:54, 10 March 2015
• Digitally-Controlled Analog Subtractive Sound Synthesis
  ...d (PCB) that implements the subtractive synthesizer. Finally, Raspberry Pi software must be developed in order to control the synthesizer's parameters in real- [[Category:System on Chips for IoTs]]
  5 KB (597 words) - 12:56, 4 December 2021
• MatPHY: An Open-Source Physical Layer Development Framework
  [[File:Setup of OsmoPHY together with RX board.png|thumb|Top: Software architecture of the MatPHY framework. Bottom: Setup of MatPHY together with ...upper layers of the OsmocomBB GSM protocol stack. The functionality of the system is verified with a testbed comprising a base station and a receiver board w
  3 KB (360 words) - 14:14, 27 May 2015
• Evolved EDGE Physical Layer Incremental Redundancy Architecture
  ...ssor and the unit where RLC blocks are processed for IR is attached to the system processor. The decoding of the RLC blocks takes place on a PHY Digital Sign ...ss Innovation Forum European Conference on Communications Technologies and Software Defined Radio (SDR-WInnComm-Europe 2013)'', pages 21–26, Munich, Germany,
  3 KB (397 words) - 14:12, 27 May 2015
• A Wireless Sensor Network for a Smart LED Lighting control
  ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.
  3 KB (487 words) - 12:02, 27 January 2016
• Ultra Low Power Wake Up Radio for Wireless Sensor Network
  ...a low power radio wake up receiver can reduce the power consumption of the system while still keeping its response time low. Another role of the wake-up radi ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe
  4 KB (613 words) - 19:54, 9 February 2015
• Infrared Wake Up Radio
  ...ices while still keeping its wake up time low. Another role of the wake-up system is that based on "intelligence" to select a specific device which has to be ...and receiver and it could include . Measurements on the performance of the system will be performed from the students in order to evaluate the distance, powe
  3 KB (515 words) - 19:55, 9 February 2015
• Audio DAC Conversion Jitter Measurement System
  ...o experienced students) comprises the implementation of such a measurement system. Possible approaches include a cross-correlating spectrum analyzer or the u : 20% Software Implementation
  2 KB (251 words) - 20:06, 17 February 2015
• Improving Scene Labeling with Hyperspectral Data
  ...uld be to evaluate and integrate this camera into a working scene labeling system [[http://dl.acm.org/citation.cfm?id=2744788 paper]] and would be very diver * create a software interface to read the imaging data from the camera
  6 KB (941 words) - 11:29, 5 February 2016
• Android Software Design
  [[File:Android Software Design.jpg|thumb]] ...processing for, e.g., heart-beat rate read-out in an ECG is desirable. The software should further include a GUI for the configuration of the data acquisition
  2 KB (278 words) - 16:57, 12 July 2022
• PULP
  [[File:pulp_block_diag.png|thumb|400px|Basic block diagram of a PULP system.]] ...d Systems] (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power e
  10 KB (1,563 words) - 10:09, 19 August 2022
• Indoor Positioning with Bluetooth
  [[Category:System Design]] [[Category:Software]]
  3 KB (449 words) - 12:12, 4 November 2019
• OpenRISC SoC for Sensor Applications
  ...r OpenRISC core with the following capabilities so that a standalone small system can be designed that can directly interface with various sensors and can co : For low power operations, we would like to shutdown most of the system including the processor, and wait until there is an event that requires the
  4 KB (667 words) - 15:23, 23 December 2016
• Hardware Accelerator for Model Predictive Controller
  In recent years reseach works shows that thermal evolution of a multicore system can be effectively modelled with linear state-space representation enabling ...will then be part of a larger system and be part of the thermal management system. In this project the goal is to implement a novel MPC algorithm in hardware
  3 KB (456 words) - 08:35, 20 January 2021
• Thermal Control of Mobile Devices
  ...s an heterogeneous thermal profile which is highly dependent on the actual system usage. As a matter of fact today and future mobile devices are thermally li ...thermal model can be directly identified from the target device by mean of system identification and self-calibrating routines.
  3 KB (452 words) - 11:03, 10 February 2015
• Real-Time Pedestrian Detection For Privacy Enhancement
  : 20% Software Development, 60% FPGA Development & Verification : or 80% software development
  3 KB (408 words) - 13:17, 5 February 2016
• Physical Layer Implementation of HSPA+ 4G Mobile Transceiver
  ...der to facilitate a cost-effective network upgrade that is based solely on software upgrade without the need for replacing the operator's network equipment. ...tionality of a standard-compliant physical layer of a mobile communication system. Possibly, the student can also investigate and analyze an interesting perf
  1 KB (159 words) - 11:16, 23 September 2016
• Digital Transmitter for Cellular IoT
  ...the first EC-GSM capable transmitter implementation worldwide (except for software defined prototypes). [1] ''Cellular system support for ultra-low complexity and low throughput Internet of Things (CIo
  3 KB (384 words) - 16:41, 17 July 2016
• Real-Time Optical Flow Using Neural Networks
  [[Category:Digital]] [[Category:Software]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Lukasc]] [ [[Category:Digital]] [[Category:System Design]]
  5 KB (707 words) - 11:22, 5 February 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...L1 scratchpad memory, and the shared main memory to optimally exploit the system's memory hierarchy and to achieve high performance.
  5 KB (716 words) - 13:43, 29 November 2019
• High-speed Scene Labeling on FPGA
  ...an ethernet adapter. As opposed to an ASIC project, such FPGA and hardware-software codesign work is much more applicable in industry and less constrained in t ...to programmable logic and design an entire hetergeneous system using with software, FPGA fabric and hardwired interfaces.
  8 KB (1,197 words) - 18:18, 29 August 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...ators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core acceler
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...erogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the e ...ators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core acceler
  4 KB (554 words) - 17:57, 7 November 2017
• Autonomous Sensing For Trains In The IoT Era
  ...ther important results will be provided by the combination of hardware and software co-design to achieve the ambitious goal of placing the smart sensor never r ...classification accuracy and energy efficiency and to further optimize the system.
  6 KB (774 words) - 08:36, 23 November 2022
• Switched Capacitor Based Bandgap-Reference
  [[Category:System Design]] [[Category:System Design]]
  4 KB (471 words) - 11:13, 3 May 2018
• Autonomous Smart Watches: Hardware and Software Desing
  ...classification accuracy and energy efficiency and to further optimize the system. : Interest in Computer Architectures at system level
  3 KB (448 words) - 11:59, 28 July 2015
• Improving our Smart Camera System
  ...hose in our prototype, and otherwise improve it by building a more compact system, adding communication capabilities to transmit suspicious cases to a remote [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]]
  8 KB (1,176 words) - 16:26, 30 October 2020
• Efficient Implementation of an Active-Set QP Solver for FPGAs
  ...essing system on the Xilinx Zynq platform, and establish the corresponding software interface. : Matlab, C++, VHDL or System Verilog
  4 KB (542 words) - 12:39, 1 June 2017
• Development of a Rockfall Sensor Node
  ...ill be performed, with the main goal to develop the complete data-grabbing software and perform real-world tests in collaboration with SLF Davos. [[Category:System Design]]
  2 KB (340 words) - 11:55, 21 August 2018
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  [[File:origami-fpga-system.png|400px|thumb]] ...o finish the processing pipeline (activation, pooling), and completing the system by connecting a camera or loading a video stream and displaying the results
  3 KB (397 words) - 18:17, 29 August 2016
• Learning Image Decompression with Convolutional Networks
  <!--[[File:origami-fpga-system.png|400px|thumb]] --> ...emester Thesis]] [[Category:Master Thesis]] [[Category:Lukasc]] [[Category:Software]] [[Category:2016]]
  2 KB (285 words) - 18:16, 29 August 2016
• Change-based Evaluation of Convolutional Neural Networks
  [[Category:Software]] [[Category:System]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2016]] * Interest in computer vision and system engineering
  5 KB (747 words) - 18:04, 29 August 2016
• Using Motion Sensors to Support Indoor Localization
  • Experience in software engineering for embedded systems [[Category:System Design]]
  3 KB (426 words) - 11:41, 21 July 2017
• Turbo Equalization for Cellular IoT
  ...wn approach to improve the overall performance of a wireless communication system. The underlying principle is to feed back soft information from the channel [[Category:System Design]]
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...w evaluation platform based on the Juno ARM Development Platform [3]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F : VHDL/System Verilog, C
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  [[Category:System Design]] [[Category:Software]]
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  [[Category:System Design]] [[Category:Software]]
  3 KB (418 words) - 14:01, 13 November 2020
• Implementation of a NB-IoT Positioning System
  ...he available NB-IoT-baseband implementation. This step includes a hardware-software co-design in which part of the algorithm will be mapped onto a PULP process : 40% Hardware/Software Co-Design (Programming in HDL and C)
  4 KB (555 words) - 16:36, 23 May 2018
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  ...ators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core acceler ...latform [3]. In a first step, the page table walker will be implemented in software as part of the kernel-level driver module. After verifying and profiling th
  5 KB (712 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...ngs of arbitrary size, independent of the page size of the Linux operating system running on the host CPU. In a student project [4], a second, set-associativ ...and give access to it to user-space applications through, e.g., an mmap() system call. Ideally, all data shared with the accelerator is placed in this secti
  6 KB (866 words) - 13:43, 29 November 2019
• Self-Learning Drones based on Neural Networks
  [[Category:Energy Efficient Autonomous UAVs]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Completed]] [[Category: * synthesis scripts & relevant software models developed for verification
  6 KB (828 words) - 16:26, 20 February 2018
• A Wireless Sensor Network for a Smart Building Monitor and Control
  ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.
  4 KB (571 words) - 21:42, 30 July 2018
• A Wearable System To Control Phone And Electronic Device Without Hands
  ..., televisions, pc among others. The main goal is to achieve an intelligent system that process the data from one or more sensors to understand the context an ...classification accuracy and energy efficiency and to further optimize the system.
  5 KB (669 words) - 17:22, 31 January 2018
• A Wireless Sensor Network for HPC monitoring
  ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors interconnected by wireless links. We want ...e power consumption reduction, reliability, functionality and optimize the system.
  5 KB (617 words) - 16:22, 27 February 2018
• LightProbe - Frontend Firmware and Control Side Channel
  ...ard-FPGA and to implement the control sidechannel interface to the backend system (a PC in our case). * Design an interface/API such that the firmware can talk to the backend system (UART based)
  3 KB (458 words) - 20:51, 12 November 2020
• Charging System for Implantable Electronics
  Using mixed-signal SoCs developed at IIS it is possible to integrate a system to conducting medical research. Despite low power consumption of the system the
  3 KB (366 words) - 13:05, 27 April 2018
• Learning Image Compression with Convolutional Networks
  <!--[[File:origami-fpga-system.png|400px|thumb]] --> ...emester Thesis]] [[Category:Master Thesis]] [[Category:Lukasc]] [[Category:Software]]
  3 KB (362 words) - 16:25, 30 October 2020
• Open Power-On Chip Controller Study and Integration
  [[Category:Software]] [[Category:Available]] [[Category:Hot]] [[Category:Semester Thesis]] [[Ca ...nodes. Computing nodes based on ARM SoCs are facing the market, as well as system based on the IBM power architecture. To create more market opportunities IB
  3 KB (462 words) - 15:57, 9 September 2016
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
  [[Category:Software]] [[Category:Available]] [[Category:Hot]] [[Category:Semester Thesis]] [[Ca ...ct access to the counter. Linux OS has already an [https://wiki.analog.com/software/linux/docs/iio/iio IIO-Subsystem] which allows to efficiently move time tra
  3 KB (417 words) - 15:55, 9 September 2016
• LightProbe - Design of a High-Speed Optical Link
  ...ansport this data-rate efficiently from the head to the backend processing system, we use a optical high-speed link. ...d software IPs. Using these IPs allows to build rather easily very complex system. You will be extensively working with the Xilinx Vivado Tool.
  3 KB (409 words) - 10:55, 10 January 2017
• PVT Dynamic Adaptation in PULPv3
  ...esis]] [[Category:2016]] [[Category:Barandre]][[Category:PULP]][[Category:System Design]] ...nts the software control loop which maximizes the energy efficiency of the system dynamically tracking the PVT variations
  3 KB (348 words) - 15:31, 13 September 2016
• Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  ...main goal of the design is to optimize the power consumption to allow the system to life several months without change the battery. THe project will be done : Interest in Computer Architectures at system level
  4 KB (502 words) - 11:38, 21 July 2017
• Efficient NB-IoT Uplink Design
  a software implementation is preferred firstly, while the transfer of specific tasks t and software can be used. The software shall be written in C and ported to the testbed with
  6 KB (900 words) - 16:58, 7 May 2018
• Sensor Fusion for Rockfall Sensor Node
  [[Category:System Software]]
  2 KB (352 words) - 11:51, 21 August 2018
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...(IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-sensor computi ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence
  9 KB (1,427 words) - 18:36, 5 September 2019
• Towards Online Training of CNNs: Hebbian-Based Deep Learning
  ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne [[Category:Software]] [[Category:Available]] [[Category:Semester Thesis]] [[Category:Hot]] [[Ca
  6 KB (909 words) - 19:50, 30 May 2017
• LightProbe
  [[File:Ultralight.jpg|thumb|400px|Current Prototype System]] * Programming of software functions: Microcontroller Programming / Processing system programming (C/C++/CUDA)
  2 KB (254 words) - 14:14, 31 October 2020
• PULP-Shield for Autonomous UAV
  [[Category:Energy Efficient Autonomous UAVs]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Completed]] [[Category: * Familiarity with embedded system programming in C.
  6 KB (875 words) - 11:06, 23 February 2018
• Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
  ...classification accuracy and energy efficiency and to further optimize the system. * Highlevel software programming, machine learning, wireless communication
  5 KB (703 words) - 17:21, 31 January 2018
• VLSI Implementation Polar Decoder using High Level Synthesis
  [[Category:System Design]] [[Category:Software]]
  3 KB (392 words) - 14:17, 5 April 2022
• FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  [[Category:System Design]] [[Category:Software]]
  3 KB (462 words) - 13:54, 13 November 2020
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  ...L implementation of HD computing for an EMG-based hand gesture recognition system with fast learning using much lower power than ever before. [[Category:System Design]]
  4 KB (467 words) - 13:38, 10 November 2020
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  * Knowledge of a hardware design language: e.g. (System)Verilog or VHDL * synthesis scripts & relevant software models developed for verification
  6 KB (842 words) - 08:37, 20 January 2021
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  The goal of this project is to develop a software application running on a PULP Chip, enabling the extraction of meaningful c The prototype system on which the source localization application will be implemented is constit
  7 KB (1,025 words) - 19:52, 30 May 2017
• A computational memory unit using phase-change memory devices
  [[Category:System Design]] [[Category:Software]]
  4 KB (546 words) - 11:33, 17 April 2020
• Deep Learning for Brain-Computer Interface
  [[Category:System Design]] [[Category:Software]]
  3 KB (372 words) - 20:22, 1 April 2019
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  [[Category:System Design]] [[Category:Software]]
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  ...evelopment. It furthermore aids in bringing up silicon quickly and makes a software developer's life a lot easier. In smaller processors like the ones develope # Specification, RTL design and host software development of a trace debugger for one of our custom RISC-V processors.
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  [[File:Hyperdimensional-Solar-System.jpg|thumb]] [[Category:System Design]]
  3 KB (366 words) - 15:39, 10 November 2020
• BigPULP: Multicluster Synchronization Extensions
  : a mixed hardware/software solution enabling lightweight, shared virtual memory (SVM) between host CPU both dramatically simplifying the programmability of such a heterogeneous system.
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  : a mixed hardware/software solution enabling lightweight, shared virtual memory (SVM) between host CPU both dramatically simplifying the programmability of such a heterogeneous system.
  6 KB (801 words) - 15:05, 23 August 2018
• Smart Virtual Memory Sharing
  initiatives such as the Heterogeneous System Architecture foundation (HSA) are access to system memory from both sides, eliminating the need for explicit
  6 KB (865 words) - 12:16, 17 November 2017
• Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
  ...detectors) to reduce the power consumption but also use energy harvesting system such as microbial fuel cell. The communication plays also an important role ...s. Other important results will be provided by combination of hardware and software co-design to achieve the ambitious goal of placing the smart sensor never r
  5 KB (745 words) - 17:21, 31 January 2018
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  [[Category:System Design]] [[Category:Software]]
  3 KB (409 words) - 13:58, 9 November 2017
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  [[Category:System Design]] [[Category:System on Chips for IoTs]]
  4 KB (460 words) - 21:42, 30 January 2018
• Satellite Internet of Things
  ...nology to cellular connectivity by covering dead spots or as a stand-alone system. NB-IoT itself is seen as a possible technology for satellite IoT (sIoT) an ...upport satellite communication channels. A thorough simulative analysis of system performance will enable the identification of critical bottlenecks. These s
  3 KB (393 words) - 13:53, 13 November 2020
• Neural Networks Framwork for Embedded Plattforms
  : 80% software development [[Category:System Design]]
  3 KB (317 words) - 14:40, 14 April 2021
• HERO: TLB Invalidation
  : a mixed hardware/software solution enabling lightweight, shared virtual memory (SVM) between host CPU both dramatically simplifying the programmability of such a heterogeneous system.
  6 KB (796 words) - 17:19, 18 November 2019
• Interference Cancellation for the cellular Internet of Things
  ...es to instant deployment scenarios, since the base stations simply needs a software upgrade. The mobile station, however, requires a redesign. The latter is no ...is a great cellular IoT research opportunity and gives deep insights into system engineering.
  2 KB (269 words) - 13:15, 31 October 2019
• Deep Convolutional Autoencoder for iEEG Signals
  ...detection and location of such seizures. When aiming a low power implanted system the large amount of data has to be efficiently reduced. iEEG signals are sp * synthesis scripts & relevant software models developed for verification
  5 KB (641 words) - 13:36, 9 September 2020
• Heterogeneous SoCs
  [[File:HERO_HW_and_SW.png|500px|thumb|right|The hardware and software stack of our Heterogeneous Embedded Research Platform (HERO).]] ...exploit their theoretical potential is challenging due to the high overall system complexity.
  3 KB (421 words) - 18:41, 28 October 2020
• Predictable Execution
  ...be deployed on COTS hardware that limit the memory interference within the system, such that real-time guarantees can be provided, enabling the use of these
  2 KB (286 words) - 18:48, 10 November 2020
• Energy Efficient Autonomous UAVs
  [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Dpalossi]] ...ize, and will thus constitute an increasingly larger fraction of the total system power consumption.
  14 KB (2,077 words) - 15:02, 13 June 2022
• Aliasing-Free Wavetable Music Synthesizer
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (621 words) - 18:09, 9 October 2022
• Modular Frequency-Modulation (FM) Music Synthesizer
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (549 words) - 12:35, 28 November 2022
• Digital Medical Ultrasound Imaging
  At IIS, we are exploring the next generation of medical ultrasound system. Our Flagship projects are: ...rable solutions as well as alternatives to the traditional bulky and rigid system designs.
  6 KB (797 words) - 16:16, 23 February 2024
• CMOS power amplifier for field measurements in MRI systems
  [[Category:System Design]] [[Category:System Design]]
  3 KB (354 words) - 16:06, 6 May 2019
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...t the FPGA hardware using Verilog or VHDL. You will use Xilinx ISE, Xilinx System Generator, Chipscope, Modelsim, Matlab and Mathamatica as development tools [[Category:System Design]]
  5 KB (599 words) - 09:03, 21 December 2017
• Inductive Charging Circuit for Implantable Devices
  [[Category:System Design]] [[Category:System Design]]
  3 KB (329 words) - 11:43, 20 August 2021
• Low Power Geolocalization And Indoor Localization
  ...classification accuracy and energy efficiency and to further optimize the system. * High-level software programming, machine learning, wireless communication
  5 KB (697 words) - 13:36, 11 January 2018
• Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
  3D sonar sensors. The proposed system architecture will be developed around an Ultra low power parallel processor * Design of the full system to achieve an autonomous sensor. (PCB design, Low power Techniques, etc.)
  4 KB (518 words) - 11:40, 2 February 2018
• Wake Up Radio For Energy Efficient Communication System and IC Design
  ...he student he can be involved on the design of the IC, the layout, or at a system and application levler. The wake-up receiver should achieves power consumpt ...classification accuracy and energy efficiency and to further optimize the system.
  5 KB (686 words) - 11:54, 2 February 2018
• Zero Power Touch Sensor and Reciever For Body Communication
  ...on the human body. The student will work to design a whole application and system exploiting the zero-power communication receiver/sensor. ...classification accuracy and energy efficiency and to further optimize the system.
  4 KB (585 words) - 11:58, 2 February 2018
• Monocular Vision-based Object Following on Nano-size Robotic Blimp
  [[Category:Hot]] [[Category:Energy Efficient Autonomous UAVs]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Available]] [[Category: * Familiarity with embedded system programming in C.
  5 KB (623 words) - 16:14, 20 February 2018
• Towards Autonomous Navigation for Nano-Blimps
  [[Category:Energy Efficient Autonomous UAVs]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Completed]] [[Category: * Familiarity with embedded system programming in C.
  7 KB (1,008 words) - 16:20, 20 February 2018
• Study and Development of Intelligent Capability for Small-Size UAVs
  [[Category:Energy Efficient Autonomous UAVs]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Completed]] [[Category: ...identified modifications to the existing system and develop the additional software tasks. Lastly, an evaluation of the proposed solution, for other architectu
  6 KB (842 words) - 16:18, 20 February 2018
• Towards Self-Sustainable Unmanned Aerial Vehicles
  [[Category:Energy Efficient Autonomous UAVs]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Completed]] [[Category: The largest part of any aerial vehicle’s power budget is the mechanical system. A blimp, however, requires significantly less power for horizontal propuls
  6 KB (914 words) - 16:17, 20 February 2018
• Biomedical Systems on Chip
  ...nce of several underlying life-long processes, e.g., respiration, vascular system dynamic, muscle contraction. ...ngs vision, the point-of-contact electronic that interfaces the biological system with the cloud-based digital world is very critical due to unique specifica
  2 KB (327 words) - 19:55, 22 February 2018
• Real-Time ECG Contractions Classification
  [[Category:Biomedical System on Chips]] ...ld you choose to accept it, is to join our active research into biomedical system design. The approach is to used state-of-the-art machine learning algorithm
  4 KB (597 words) - 19:15, 9 March 2020
• Predictable Execution on GPU Caches
  ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...collaborating with research groups and companies around Europe to create a software framework for timing predictable execution on commercial off-the-shelf (COT
  5 KB (706 words) - 17:41, 19 June 2019
• Freedom from Interference in Heterogeneous COTS SoCs
  ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...collaborating with research groups and companies around Europe to create a software framework for timing predictable execution on commercial off-the-shelf (COT
  4 KB (499 words) - 17:40, 19 June 2019
• Pulse Oximetry Fachpraktikum
  : Experience with hardware design and embedded software is advantageous : 30% Software
  3 KB (358 words) - 15:59, 18 February 2019
• Wearables for Sports and Life Enhancement
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  3 KB (381 words) - 14:17, 28 January 2023
• Engineering For Kids
  ...studies in (primary+) schools we're developing an interesting edutainment system for kids together with the PR of D-ITET and [http://www.wysszurich.uzh.ch w The idea is to create a playful, central interaction system accompanied by distributable modules for the kids to solve and play with.
  3 KB (447 words) - 16:11, 18 September 2018
• OTDOA Positioning for LTE Cat-M
  ...f needed dedicated hardware blocks can be deisgned and integrated into the system. If time allows the performance of the implementation will be verified with : 40% Hardware/Software Co-Design (Programming in HDL and C)
  4 KB (566 words) - 15:50, 9 February 2021
• Optimal System Duty Cycling for a Mobile Health Platform
  ...hanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level d ...dictates battery size, the most critical factor in any volume-constrained system.
  4 KB (597 words) - 16:57, 12 July 2022
• Design and Implementation of a multi-mode multi-master I2C peripheral
  ...and not in the chips that we designed ourselves, rendering many low-level system management jobs challenging and cumbersome. In this project, you will exten *Some experience with hardware design (VHDL/(System-)Verilog), for example completion of VLSI I lecture
  2 KB (240 words) - 16:57, 12 July 2022
• Enabling Standalone Operation for a Mobile Health Platform
  ...iomedical acquisition and processing platform is standalone operation: The system must be able to provide all required supply voltages and clock frequencies ...ject you are going to put them all together and create the missing control software/firmware. The goal is to demonstrate startup and operation of the platform
  2 KB (268 words) - 16:57, 12 July 2022
• Embedded Gesture Recognition Using Novel Mini Radar Sensors
  ...classification accuracy, and energy efficiency and to further optimize the system. * High-level software programming, machine learning, wireless communication
  5 KB (631 words) - 15:36, 10 November 2020
• Physics is looking for PULP
  ...ring this project you will map a 32bit PULPino/PULPissimo micro-controller system to the Altera DE-10 Lite board, adapt the design flow so that prospective u [[Category:System Design]]
  4 KB (497 words) - 16:50, 21 June 2018
• Human Intranet
  ...with the functions provided by the body itself. Human Intranet presents a system vision in which, for example, disease would be treated by chronically measu * '''System-level design and testing''' (Altium, C-programming)
  17 KB (2,419 words) - 20:09, 10 March 2024
• Positioning for the cellular Internet of Things
  ...rrival (OTDOA) such as covered in [[Implementation of a NB-IoT Positioning System]] or [[OTDOA Positioning for LTE Cat-M]] * Positioning server software development
  1 KB (204 words) - 13:14, 31 October 2019
• Low Latency Brain-Machine Interfaces
  ...r rhythms (SMR) and movement-related cortical potentials (MRCP). SMR-based system make use of event-related synchronisation/desynchronisation (ERD/ERS) behav * synthesis scripts & relevant software models developed for verification
  4 KB (594 words) - 09:18, 16 September 2021
• A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  ..., non-invasive method to measure kidney performance via an external sensor system to avoid the use of urinary catheters for this subgroup of patients, thereb ...classification accuracy, and energy efficiency and to further optimize the system. The work includes the modeling and design of a suited impedance sensor, it
  6 KB (857 words) - 15:37, 10 November 2020
• Indoor Smart Tracking of Hospital instrumentation
  ...ional demands on hospital staff. The goal of the project is set-up a whole system that includes readers and mobile tags. For example in the case of the RFID, * High-level software programming, signal processing, machine learning, wireless communication
  6 KB (780 words) - 15:37, 10 November 2020
• Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
  ...be to capture the raw sensor data and transfer it to a PC system for fully software-defined processing, offering unprecedented flexibility and enabling new ima ...we at IIS have demonstrated that this novel architecture is feasible for a system with 64 channels ([[LightProbe]]), it yet has to be demonstrated that this
  2 KB (250 words) - 20:48, 12 November 2020
• Wireless Sensing With Long Range Comminication (LoRa)
  ...esinged node will also include energy harvesting to allow a self-sustainig system. * High-level software programming, signal processing, machine learning, wireless communication
  5 KB (744 words) - 15:37, 10 November 2020
• AMZ Driverless Competition Embedded Systems Projects
  '''Embedded stereo visual inertial system''' ...omputing system. In addition, some image processing should be done at this system to reduce the overhead of the network and to compute the first steps on the
  6 KB (895 words) - 16:27, 30 October 2020
• Edge Computing for Long-Term Wearable Biomedical Systems
  ...eting two application scenarios: behind-the-ear EEG and ECG wristband. The system will also be used to explore applications scenarios for augmenting current * High-level software programming, signal processing, machine learning, wireless communication
  6 KB (761 words) - 15:38, 10 November 2020
• Elliptic Curve Accelerator for zkSNARKs
  ...esearch tries to improve the performance of these Zero Knowledge Proofs in software but without significant improvements, it is impossible to create a proof on [[Category:System Design]]
  5 KB (614 words) - 15:02, 4 March 2019
• Outdoor Precision Object Tracking for Rockfall Experiments
  * High-level software programming, signal processing, machine learning, sensor fusion, wireless c [[Category:System Design]]
  5 KB (714 words) - 08:37, 23 November 2022
• Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  ...roject focusses on the development of an unobtrusive multisensory embedded system to assist coaches to better quantify jumping trajectories of athletes. With ...perceptible to the athlete so as not to disturb his/her sensitive jumping system.
  6 KB (820 words) - 12:13, 23 July 2023
• Energy Efficient AXI Interface to Serial Link Physical Layer
  ...d data compression. The project will require simulation and testing of the system to verify its performance, power consumption, and compatibility with differ * Experience with System Verilog or Verilog, VLSI 1
  2 KB (250 words) - 18:21, 20 February 2023
• Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  ...are, we can guarantee a high flexibility of the setup. This means that the system can be adapted in operation for a wide variety of transducer types and setu ...he characterization and tuning of ultrasonic transducers both in hard- and software.
  5 KB (644 words) - 18:18, 21 July 2023
• NAND Flash Open Research Platform
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (551 words) - 11:06, 11 July 2019
• A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
  ...sor hardware which consists of an ATMEL [2] chip connected with an FPGA. A software defined radio receives (SDR) the signal of multiple sensor nodes. The signa ...A, configuration of the SDR, and the evaluation in Matlab. Eventually, the system has to be tested thoroughly.
  5 KB (731 words) - 16:42, 27 August 2019
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (517 words) - 17:09, 16 September 2021
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  ...propose to build the next OPEN-SOURCE RISC-V programmable smart-peripheral system for the Ariane Core. ...crocontroller as for example the Raspberry-Pi or the Ariane core makes the software portability and reusability easy.
  7 KB (1,030 words) - 19:05, 29 January 2021
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
  ...n innovative class of hardware accelerators with improved cooperation with software, high energy efficiency and much greater flexibility than ...is thesis, you will design a novel heterogeneous interconnect for the PULP system to connect high-throughput hardware accelerators to
  7 KB (961 words) - 21:21, 29 January 2019
• Timing Channel Mitigations for RISC-V Cores
  ...act''' [Ge2018a], [Ge2018b]. Security is and has always been the operating system's (OS) job. For instance, memory protection is already well established - ' ...hardware design and computer architecture -- having followed the "Advanced System-on-Chip Design" or "Energy-Efficient Parallel Computing Systems for Data An
  6 KB (915 words) - 18:16, 20 May 2020
• Developing a small portable neutron detector for detecting smuggled nuclear material
  [[Category:System Design]] [[Category:System on Chips for IoTs]]
  5 KB (623 words) - 10:32, 5 November 2019
• ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
  ...ct the way biomechanical measurements are performed today, as the proposed system should be easy and quick to use (e.g., time is key for testing patients in [[Category:System on Chips for IoTs]]
  6 KB (735 words) - 12:12, 23 July 2023
• Floating-Point Divide & Square Root Unit for Transprecision
  ...ly. In contrast to approximate computing where the precision of the entire system is reduced - often incurring loss in result quality - transprecision comput * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx
  8 KB (1,135 words) - 17:09, 29 July 2020
• FPGA Testbed Implementation for Bluetooth Indoor Positioning
  ...he Bluetooth LE digital baseband block. Then you will develop the required software to interface the digital baseband block and if needed extend the hardware t
  3 KB (431 words) - 21:47, 18 November 2019
• Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
  ...he occurrence of ionization events due to cosmic radiation. The monitoring system has to acquire the frequency of the ionizing events and the amount of the c : • Design the monitoring system
  4 KB (493 words) - 16:31, 5 June 2019
• Heroino: Design of the next CORE-V Microcontroller
  ...ence easy and standard, with industrial standard peripherals subsystem and software (as freeRTOS). **system:
  9 KB (1,314 words) - 00:01, 7 February 2021
• PREM Intervals and Loop Tiling
  ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory
  4 KB (531 words) - 18:00, 19 June 2019
• Compiler Profiling and Optimizing
  ...ification is to provide guarantees on freedom from interference within the system, enabling strict guarantees on the completion of real-time tasks before the ...memory system at one point in time. To avoid stalling the program when the system is not permitting memory accesses from the program in question, the memory
  3 KB (466 words) - 18:20, 19 June 2019
• Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
  ...ter thesis between IIS and Hilti that includes the desing of new hardware-software devices. In particular, machine learing, energy harvesting, bluetooth commu ...E capacitive sensing: pass information across an air gap. Design analogous system to perform a measurement task. For reference: https://www.st.com/en/solutio
  5 KB (645 words) - 15:41, 10 November 2020
• Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
  ...ovel Parallel processots (PULP). The student will design both hardware and software, including deep learning algorithms. The Wearable camera has been carefull * Motivation to build and test a real system
  4 KB (519 words) - 15:41, 10 November 2020
• Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
  ...nd hot topic investigation on the adversarial attack for both hardware and software, including the possible ottimization of deep learning algorithms. In partic * Motivation to build and test a real system
  4 KB (509 words) - 15:41, 10 November 2020
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  ...hole working embedded system. The student will deal with both hardware and software building a prototype to cover a specifc application. Hardware-software projects suggestions
  5 KB (692 words) - 15:45, 10 November 2020
• Manycore System on FPGA (M/S/G)
  <!-- Manycore System on FPGA --> * Software
  8 KB (1,319 words) - 10:41, 6 July 2021
• Hardware Acceleration
  ...essors. This ''separation of compute acceleration and control'' limits the system's flexibility and real-world performance as communication and data exchange ...ral-purpose cores directly''. This can be done either by writing optimized software for specific problems, or by integrating dedicated acceleration hardware ''
  7 KB (917 words) - 17:04, 24 November 2023
• Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
  : 80% System Development [[Category:System on Chips for IoTs]]
  5 KB (584 words) - 12:09, 29 October 2020
• TCNs vs. LSTMs for Embedded Platforms
  ...performing one, the student will proceed with embedded implementation and system integration in order to demonstrate a real-life application using sensor ac : 80% Software Development
  2 KB (317 words) - 11:10, 21 July 2020
• BirdGuard
  ...as a basis for prototyping the BirdGuard algorithms and the deterrence sub-system. Swiss research institutes are at the forefront of researching birds and ap The BirdGuard system aims to complement existing passive approaches by providing an easy-to-use
  5 KB (647 words) - 08:32, 23 February 2023
• Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
  ...ly transmitting, easy to install and cost-effective for wind turbines. The system will integrate novel embedded signal processing solutions, including artifi ...classification accuracy, and energy efficiency and to further optimize the system. Energy Harvesting can be also employed to design the sensor node, and this
  5 KB (737 words) - 15:48, 10 November 2020
• Semi-Custom Digital VLSI for Processing-in-Memory
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  7 KB (882 words) - 14:33, 28 July 2021
• Hyper-Dimensional Computing Based Predictive Maintenance
  * Some experience in software development using Python * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx
  5 KB (759 words) - 09:18, 16 September 2021
• Accurate deep learning inference using computational memory
  [[Category:System Design]] [[Category:Software]]
  5 KB (628 words) - 12:51, 17 April 2020
• ASIC Implementation of Jammer Mitigation
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (662 words) - 13:31, 10 May 2023
• Real-Time Motor-Imagery Classification Using Neuromorphic Processor
  ...ented in a neuromorphic processor, and none of them are presenting a whole system from the data acquisition to the processing. ...of the present project is to investigate and develop a novel neuromorphic system for Brain–computer interfaces, trained for multi-class motor-imagery, th
  6 KB (815 words) - 20:02, 10 March 2024
• Compression of iEEG Data
  ...detection and location of such seizures. When aiming a low power implanted system the large amount of data has to be efficiently reduced. iEEG signals are sp * synthesis scripts & relevant software models developed for verification
  5 KB (636 words) - 20:01, 10 March 2024
• Improved State Estimation on PULP-based Nano-UAVs
  [[Category:Hot]] [[Category:Energy Efficient Autonomous UAVs]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Completed]] [[Category: ...ehicles. There are several embodiments of the PULP paradigm, one of them a system-on-chip (SoC) called ''Mr.Wolf''[5]. This SoC features 9 cores, divided int
  8 KB (1,117 words) - 22:17, 26 January 2022
• Deep Learning-based Global Local Planner for Autonomous Nano-drones
  ...[[Category:Energy Efficient Autonomous UAVs]] [[Category:UAV]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Available]] [[Category: [[File:GL_dpalossi.png|thumb|right|1000px|Overview of the cyber-physical system.]]
  4 KB (571 words) - 12:11, 27 January 2022
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  ...oughput and are at least one order of magnitude more energy efficient than software implementations of these algorithms, they all make use of static random acc ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended
  7 KB (1,032 words) - 15:31, 16 November 2020
• High Performance SoCs
  ...oncept.png|thumb|350px|Concept art for ''Manticore'', a Snitch-based 22 nm system with 4096 cores on multiple chiplets and with HBM2 memory.]] ..., ensuring high performance requires us to consider the '''entire hardware-software stack''':
  11 KB (1,337 words) - 10:54, 25 January 2024
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
  <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> * 10% Software / Tooling
  11 KB (1,675 words) - 15:40, 15 March 2021
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
  * 20% Software / Tooling ...0px|alt=A HERO system with a Zynq MPSoC coupled to a Snitch cluster|A HERO system with a Zynq MPSoC coupled to a Snitch cluster]]
  11 KB (1,617 words) - 23:59, 6 February 2021
• Peak-to-average power Reduction
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (513 words) - 14:16, 24 November 2021
• Software-Defined Paging in the Snitch Cluster (2-3S)
  ...the page is available'''; the necessary page replacement be done fully in software on the DMA core. * '''Optimize the hardware and software''' in accordance with your evaluation.
  4 KB (563 words) - 20:08, 15 February 2021
• VLSI Implementation of a 5G Ciphering Accelerator
  [[Category:System Design]] [[Category:Software]]
  3 KB (404 words) - 10:05, 9 February 2021
• Time Gain Compensation for Ultrasound Imaging
  The [[LightProbe]] system is designed to acquire ultrasound data for many different applications (e.g ...of LightProbe, you will identify the approach to use to include TCG in the system, and, once implemented, you will perform ultrasound test measurements on ph
  2 KB (318 words) - 16:58, 16 September 2022
• IP-Based SoC Generation and Configuration (1-3S/B)
  ...IPs is the norm, but becomes more difficult and error-prone the larger the system becomes. ...simply a loose collection of scripts and templates shipped with the Snitch system [https://github.com/pulp-platform/snitch]. You will
  4 KB (617 words) - 10:19, 3 November 2023
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.
  8 KB (1,196 words) - 10:41, 6 July 2021
• Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
  ...ature extraction, and since it has been showed that the performance of the system can be largely influenced by this choice, the aim of this project is to do ...representation of the signal to the actual response of the human auditory system. The derivation techniques are described in detail in [[#ref-lyonmfcc|&#91;
  13 KB (1,815 words) - 13:31, 15 February 2024
• Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
  : 80% System Development [[Category:System on Chips for IoTs]]
  8 KB (931 words) - 17:27, 23 November 2021
• MemPool on HERO (1S)
  ...amming model simple and portable and enables accelerating state-of-the-art software and benchmarks.HERO currently uses the Parallel Ultra-Low Power (PULP) clus ...ftware to interact with a PMCA, such as MemPool. In this step, the MemPool system will be integrated and connected to HERO’s accelerator interface.
  6 KB (902 words) - 19:07, 20 January 2021
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  * Synthesize your controller and the surrounding system; create area and timing reports. * Implement your system on an ASIC and tape it out.
  8 KB (1,214 words) - 15:18, 9 July 2021
• ISA extensions in the Snitch Processor for Signal Processing (M)
  .../>[[#ref-RISCV_P|8]]]. The set of instructions that should be added to the system is not fixed, but the student should implement and evaluate different image
  9 KB (1,311 words) - 00:08, 13 March 2021
• Cell-Free mmWave Massive MIMO Communication
  A cell-free system is a network formed by distributed access points (APs) over a large area co ...tudied in [3]. Last, to solve the lack of usage of all APs in this type of system, [4] presents an energy efficient AP sleep mode-technique that is able to d
  7 KB (882 words) - 21:34, 13 July 2022
• Practical Reconfigurable Intelligent Surfaces (RIS)
  [[File:Image_RIS.png|400px|thumb|RIS aided wireless system.]] In [1], a RIS is used in the downlink of a MIMO system to investigate the improvement provided by these devices in terms of energy
  8 KB (1,011 words) - 12:25, 16 November 2023
• Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (653 words) - 11:08, 12 November 2020
• Low-Resolution 5G Beamforming Codebook Design
  ...the signals transmitted by the individual antenna elements, providing the system with the capability to “beamform,” that is, to control the direction an : 70% System development
  6 KB (829 words) - 11:37, 12 November 2020
• Deep Unfolding of Iterative Optimization Algorithms
  ...the project is to then implement Deep Unfolding on a resource-constrained system, like a Raspberry Pi. This project requires familiarity with calculus and p : 50% Software implementation
  6 KB (748 words) - 13:57, 12 November 2020
• ASIC Development of 5G-NR LDPC Decoder
  [[Category:System Design]] [[Category:Software]]
  3 KB (389 words) - 01:43, 10 February 2021
• Autonomus Drones With Novel Sensors And Ultra Wide Band
  ...as complete autonomous drones. The students will follow the full flow from system design to firmware implementation and they can also deal with machine learn * A complete hardware and software prototype of drones and smart sensor system, which includes all the subsystems (sensor acquisition, preprocessing, and
  5 KB (646 words) - 11:39, 30 November 2020
• Smart Patch For Heath Care And Rehabilitation
  ...a team, they will learn how to structure problems and identify solutions, system analysis, and simulation, as well as presentation and documentation techniq * A complete hardware and software prototype of drones and smart wearable device, which includes all the subsy
  7 KB (1,033 words) - 16:24, 30 November 2020
• Short Range Radars For Biomedical Application
  ...hardware, on the data acquisition, on the hardware design, on the hardware-software co-design or in all of them (i.e. in the case of a master thesis) . Moreove ...ncrease the response time of the detection, aiming to achieve an always-on system.
  5 KB (692 words) - 12:46, 17 December 2021
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  ...onnecting 4 Baikonur ASICs through their serial links, creating a 104-core system with both application- and HPC-grade cores. ...onality. However, a lot of work still needs to be done to ''bring up'' the system so we can turn use it as an impressive evaluation and demonstration platfor
  11 KB (1,602 words) - 15:19, 9 July 2021
• Efficient Synchronization of Manycore Systems (M/1S)
  * 20% Software ...his coordination can limit the potential speedup offered by the multi-core system according to Amdahl’s law [[#ref-Hennessy2017|&#91;1&#93;]]. Efficient m
  12 KB (1,864 words) - 12:08, 29 August 2022
• Transforming MemPool into a CGRA (M)
  * 40% Software ...ool’s flexibility by having a duality of modes. The result is a flexible system that achieves a very high throughput for systolic workloads.
  13 KB (1,887 words) - 15:51, 17 November 2021
• Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
  ...n tasks to improve maturity and extend the current feature set, as well as software development in the form of Linux driver development. ...signed and integrated into processing systems, as well as how to establish software support for them both in bare-metal applications and under Linux.
  7 KB (1,122 words) - 15:21, 9 July 2021
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  ...CB for the iCE40 family to facilitate measurements and/or demonstrate your system in action. Can we compete with a microcontroller in terms of performance an ...s, nevertheless the use of LaTeX with Inkscape or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
  8 KB (1,220 words) - 15:18, 9 July 2021
• LLVM and DaCe for Snitch (1-2S)
  * Extending DaCe to generate efficient code for a Snitch system from SDFGs, ideally for the existing Snitch-HERO platform. ...isting C++ DaCe backend to emit LLVM-compilable code for a manycore Snitch system like Snitch-HERO. Validate your implementation on simple kernels or selecte
  11 KB (1,519 words) - 15:20, 9 July 2021
• Efficient TNN Inference on PULP Systems
  ...pport for sub-byte arithmetic operations (e.g., 16x2b MAC) and construct a system around the improved core, which will be taped out. You get to build your ow ...implement an efficient framework for executing TNNs. They will start with software support for the baseline architecture with the pre-existing ISA extensions.
  5 KB (768 words) - 15:14, 4 August 2022
• Online Learning of User Features (1S)
  ...e user’s characteristics can considerably improve the performance of the system. We want to explore how the user-specific features can be exploited in orde ...ility of those features belonging to a certain class. A schematic of a KWS system can be seen in Figure 1.
  11 KB (1,610 words) - 11:00, 14 November 2022
• Huawei Research
  ...mental research in the area of future computing systems (new hardware, new software, new algorithms). *General interest in Deep Learning and memory/system design
  6 KB (799 words) - 11:11, 1 August 2022
• Ultrasound
  ...work on the development of hardware and software for a complete biomedical system.
  797 bytes (90 words) - 16:37, 23 February 2022
• Hardware/software codesign neural decoding algorithm for “neural dust”
  ...ires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for ...while reducing the damage caused by the implantation [1][2]. However, such system also poses stringent constraints on the power consumption and area.
  4 KB (519 words) - 16:16, 9 January 2023
• Spiking Neural Network for Motor Function Decoding Based on Neural Dust
  ...ires brain activity and translates the information into actions to control software and hardware such as computers and prostheses. As a potential treatment for 2. Get familiar with the dataset, the system, and the deep learning framework
  5 KB (662 words) - 20:05, 10 March 2024
• Fast Simulation of Manycore Systems (1S)
  At ETH, we are developing our own many-core system called MemPool [[#ref-Cavalcante2020|&#91;1&#93;]], [[#ref-Riedel2021|&#91 ...y rely on cycle-accurate RTL simulation. However, simulation of such a big system is slow, even on the latest commercial simulators. This limits the complexi
  10 KB (1,434 words) - 17:20, 2 August 2021
• Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  At ETH, we are developing our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme This manycore system with vector support is to be analyzed in terms of the performance improveme
  11 KB (1,609 words) - 10:00, 30 June 2022
• Novel Methods for Jammer Mitigation
  ...uous operability is of critical importance. An important asset of wireless system is therefore the ability to mitigate attacks by jammers that try to disrupt ...oped in our group. The project will also involve mathematical analysis and system-level simulations. This project requires a solid background in statistics a
  6 KB (687 words) - 13:32, 10 May 2023
• Probing the limits of fake-quantised neural networks
  ...QNNs use floating-point operands to leverage the optimised floating-point software kernels provided by the chosen deep learning frameworks. [[Category:System on Chips for IoTs]]
  5 KB (659 words) - 14:08, 15 February 2024
• Feature Extraction for Speech Recognition (1S)
  ...ature extraction, and since it has been showed that the performance of the system can be largely influenced by this choice, the aim of this project is to do ...representation of the signal to the actual response of the human auditory system. The derivation techniques are described in detail in [[#ref-lyonmfcc|&#91;
  12 KB (1,688 words) - 11:00, 14 November 2022
• Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
  ...ware-constrained devices, expanding the capabilities of a keyword spotting system. ...pervised information. This is possible due to the prior knowledge that the system has over the nature of the data that it is presented with, and it is a spec
  12 KB (1,869 words) - 17:37, 1 September 2023
• Modular Distributed Data Collection Platform
  ...e:motivation_sensor.png|200px|thumb|right|Example of remote controlled DAQ system]] ...to remote control the local data acquisition. Regarding energy supply, the system should be designed as a hybrid solution. It will incorporate a battery-powe
  4 KB (467 words) - 12:58, 20 July 2023
• VLSI Design of an Asynchronous LDPC Decoder
  ...due to the availability of easy-to-use electronic design automation (EDA) software that significantly facilitates circuit design. The main drawback of synchro [[Category:System on Chips for IoTs]]
  6 KB (725 words) - 17:36, 20 October 2021
• Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  ...magined by the user by means of BCI devices. Once fully functional, such a system would be of immeasurable value in the design of, e.g., motorized prostheses * synthesis scripts & relevant software models developed for verification
  8 KB (1,101 words) - 20:04, 10 March 2024
• XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  7 KB (933 words) - 19:29, 21 November 2021
• Robert Balas
  ...rdware design, operating system and hacking the compiler. I'm an avid free software contributor, GNU/Linux and Emacs user. I'm https://github.com/bluewww on Gi
  931 bytes (108 words) - 10:30, 22 November 2021
• Integrating Hardware Accelerators into Snitch (1S)
  ...] and the floating-point repetition (FREP) hardware loop, which allows the system to achieve FPU utilization above 90%. ...erators that share the memory with the general-purposed cores and that are software-programmed by the cores. A plethora of HWPEs have been developed at our gro
  4 KB (567 words) - 13:57, 7 September 2022
• Flexfloat DL Training Framework
  ...out a slightly smaller version of Manticore, called Occamy, a two-chiplet system in the near future. Snitch-based architectures are built around the minimal ...vertheless, the use of LaTeX with Tgif, drawio or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
  4 KB (613 words) - 10:13, 2 November 2022
• Non-blocking Algorithms in Real-Time Operating Systems
  ...ing to allow high priority interrupts to get the highest attention. On the software-level you try to keep interrupt handling routines and critical sections as ...on primitives used in FreeRTOS [4] [5], an open-source real-time operating system (RTOS) used by Amazon, and determine how they use critical sections. Turn t
  4 KB (508 words) - 18:59, 10 January 2022
• Real-Time Embedded Systems
  ...ical instant''' at which these results are produced. In fact, a real-time system changes its state as a function of physical time. ...controlled object'' (the ''controlled cluster''), the ''real-time computer system'' (the ''computational cluster'') and the ''human operator'' (the ''operato
  4 KB (518 words) - 09:54, 10 January 2022
• Implementing DSP Instructions in Banshee (1S)
  ...highly-parallelizable algorithms. Exploring new architectures and writing software for manycore systems is very challenging and requires the support of good s ==== Software Code Style ====
  10 KB (1,428 words) - 13:31, 27 October 2022
• Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  7 KB (804 words) - 19:45, 21 November 2021
• Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
  <!-- Peripheral Event Linking System For Real-Time Capable Energy-Efficient SoCs (M/1-2S) --> ...essing. Its\u2019 aim is the development of an open, scalable hardware and software research and development platform with the goal to break the energy efficie
  8 KB (1,127 words) - 19:54, 1 March 2023
• HW/SW Safety and Security
  ...Embedded Systems]] if you are interested in designing hardware or writing software for timing predictable embedded systems. [[File:Mcs.png|thumb|350px| A Mixed Criticality System (MCS).]]
  5 KB (614 words) - 09:49, 15 January 2024
• Low Resolution Neural Networks
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (520 words) - 14:52, 24 November 2021
• Watchdog Timer for PULP
  ...tware malfunction, the WDT will not be properly serviced, resulting in the system returning to its original state. * Properly verify the WDT, both with regular testbenches as well as software tests in the PULPissimo SoC
  2 KB (337 words) - 08:49, 21 June 2022
• PULP’s CLIC extensions for fast interrupt handling
  ...ding environment, for example external master devices interacting with the system through I/O peripheral interfaces. This means that the underlying HW has to * 20% Software layer
  4 KB (515 words) - 15:06, 5 August 2022
• Fast Accelerator Context Switch for PULP
  ...ization capabilities to the cluster of ControlPULP, allowing the operating system to schedule several accelerator tasks and let them run concurrently. This a * Implement context switching capabilities in software as a baseline.
  6 KB (835 words) - 16:27, 7 July 2023
• Development of a fingertip blood pressure sensor
  *Software/data analysis/signal processing, based of existing sensor data, developing *Software/firmware, translating the created data model into embedded C code and devel
  4 KB (535 words) - 16:56, 12 July 2022
• Passive Radar for UAV Detection using Machine Learning
  ...with the goal of verifying the effectiveness and practicability of such a system, which will answer the question of whether reliable UAV detection is indeed : 20% System-level simulation
  5 KB (564 words) - 16:12, 9 February 2022
• Through Wall Radar Imaging using Machine Learning
  ...ill assess the efficacy of such ML-based methods using real-world data and software simulations. The project will be carried out in collaboration with the Swis : 20% System-level simulation
  5 KB (586 words) - 16:15, 9 February 2022
• Improved Collision Avoidance for Nano-drones
  ...[[Category:Energy Efficient Autonomous UAVs]] [[Category:UAV]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Available]] [[Category: [[File:ToFDrone_dpalossi.png|thumb|right|500px|Overview of the cyber-physical system.]]
  4 KB (550 words) - 21:25, 15 February 2022
• Bridging QuantLab with LPDNN
  QuantLab is a PyTorch-based software tool aiming to enable the exploration and comparison of different quantisat ...udent and the advisors will also have bi-weekly code reviews to ensure the software contributions are properly aligned with both QuantLab and LPDNN, streamlini
  7 KB (831 words) - 19:36, 12 January 2023
• Exploring NAS spaces with C-BRED
  * 10% Software engineering [[Category:System on Chips for IoTs]]
  6 KB (839 words) - 14:08, 15 February 2024
• Low-Complexity MIMO Detection
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (503 words) - 13:54, 30 May 2022
• Forward error-correction ASIC using GRAND
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (470 words) - 18:16, 27 May 2022
• Low-power time synchronization for IoT applications
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  4 KB (492 words) - 10:55, 16 June 2022
• Weak-strong massive MIMO communication with low-resolution ADCs
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (662 words) - 13:33, 10 May 2023
• Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
  At ETH, we developed our own many-core system called MemPool. It boasts 256 lightweight 32-bit Snitch cores. They impleme ...d to integrate an FLL, a boot ROM, and a JTAG to access and initialize the system. While there are many IPs and know-how at IIS for that, this is also highly
  8 KB (1,239 words) - 12:36, 29 January 2024
• Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (586 words) - 15:34, 11 July 2022
• Event-based navigation on autonomous nano-drones
  ...[[Category:Energy Efficient Autonomous UAVs]] [[Category:UAV]] [[Category:Software]] [[Category:Digital]] [[Category:PULP]] [[Category:Available]] [[Category: ...to run on a novel ultra-low-power processor, such as the PULP Kraken [3,4] System-on-Chip (SoC). At the same time, the candidate will also work on the hardwa
  4 KB (505 words) - 18:25, 26 July 2022
• Zephyr RTOS on PULP
  ...l). Among these, Zephyr OS [1] is a promising scalable real-time operating system with small memory footprint designed for resource-constrained systems follo ...required to be able to track and set the operating point of the controlled system in a workload-aware manner.
  3 KB (483 words) - 15:28, 19 February 2024
• PULP Freertos with LLVM
  ...required to be able to track and set the operating point of the controlled system in a workload-aware manner. Currently, we support FreeRTOS [5] in ControlPULP as real-time operating system using our custom compiler toolchain based on GCC [3] which supports various
  3 KB (438 words) - 16:51, 5 August 2022
• Running Rust on PULP
  [[Category:Software]] ...s of more modern languages. This allows for easier design of more advanced software. Instead of directly handling memory, Rust operates on a principle of owner
  2 KB (311 words) - 14:14, 29 June 2023
• Implementing Configurable Dual-Core Redundancy
  At ETH, we are developing our own many-core system called MemPool [[#ref-Cavalcante2020|&#91;2&#93;]], [[#ref-Riedel2021|&#91; * 20% Hardware and Software familiarization
  4 KB (497 words) - 14:15, 29 June 2023
• Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
  WP2: Software Development (8 weeks, September-October) WP3: System Development and HW Extension (8 weeks, November-December)
  4 KB (549 words) - 11:35, 3 November 2023
• MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
  [[Category:Computer and System Architecture]] ...ircuits and FPGAs thanks to their versatility and easy programmability via software routines typically written in the C language.
  8 KB (1,304 words) - 14:44, 23 October 2023
• A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
  This project involves both creating the FPGA platform and extending the software stack (e.g. Linux) running on the ASIC to use it. ====== Software Design ======
  3 KB (416 words) - 10:49, 25 January 2024
• Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
  ...ed Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Integration (2S,1M) --> ...ople.ee.ethz.ch/~janniss/projects/Maddness_system_integration.pdf Maddness System Intergration]
  6 KB (846 words) - 16:50, 3 November 2022
• Alias-Free Oscillator Synchronization for Arbitrary Waveforms
  ...is widely used in modern music production, with many popular hardware and software synthesizers from Roland, Nord Keyboard, Waldorf, Native Instruments, Artur [[Category:System on Chips for IoTs]]
  5 KB (577 words) - 09:48, 5 October 2022
• Audio Visual Speech Separation and Recognition (1S/1M)
  ...er(s) with the transcript of their respective speech. Lastly, the proposed system must abide by the TinyML[[#ref-reddi2020|&#91;5&#93;]] constraints consider ...en/information/how-to/drawing-schematics.html) or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
  11 KB (1,467 words) - 14:15, 1 March 2024
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  ...ta movement between the L2 and L1 memories has to be explicitly defined in software, for which several DMA engines are provided. This design decision improves ...timize the kernels to take advantage of the heterogeneous architecture and software defined data movement. An additional goal would be to explore the applicabi
  7 KB (944 words) - 10:47, 25 January 2024
• Runtime partitioning of L1 memory in Mempool (M)
  ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me * In the first part you will be asked to adapt a software approach to the problem, working on the dynamic allocation of data structur
  3 KB (490 words) - 10:38, 2 November 2023
• Radiation Testing of a PULP ASIC
  ...ame room. As access to the room will be limited during the experiment, the system should be designed to allow us to sample as much data as possible during th * software for a simple computer to reliably control and program the chip, and log any
  3 KB (454 words) - 14:59, 25 October 2023
• AXI-based Network on Chip (NoC) system
  <!-- AXI-based Network on Chip (NoC) system --> ...ystem integration for a potential tapeout. For the verification, low-level software and drivers should be written and tested
  2 KB (252 words) - 14:43, 23 October 2023
• All the flavours of FFT on MemPool (1-2S/B)
  ...L1 data-memory. Leveraging its hierarchical architecture, we can scale the system to TeraPool, a cluster of 1024 Snitch cores, having 4096 banks of shared me * 50% Software Design
  3 KB (460 words) - 18:54, 9 November 2022
• Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
  ...d Spatz on the TeraPool architecture as our hardware platform, a scaled-up system from MemPool [[#ref-Cavalcante2020|&#91;2&#93;]], which has 1024 Snitch cor ...r utilization, aiming to extract the maximum possible performance from the system.
  6 KB (775 words) - 11:57, 31 October 2023
• Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
  ...the voter detects discrepancy in the results, it alerts the system that a system failure happened and recovery or reset procedures must be initiated. ...the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and p
  5 KB (752 words) - 13:23, 24 October 2023
• Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
  ...igh flexibility: hardware compute units can be re-configured (possibly via software) to act as general-purpose or specialized processing engines. ...reconfigurable vector processor cluster to optimize area footprint of the system;
  5 KB (651 words) - 20:42, 22 November 2022
• Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
  * Integrate the IP into a full SoC system through an AXI-based DMA controller; ...the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and p
  5 KB (631 words) - 09:28, 3 November 2023
• Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
  * Integrate the peripheral into a full SoC system; ...the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and p
  4 KB (554 words) - 09:28, 3 November 2023
• Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
  Epilepsy is a central nervous system disorder characterized by abnormal brain activity, causing seizures or peri ...ilst not forgetting the properties of previous users that might re-use the system; thus, our model must mitigate the "catastrophic forgetting" phenomenon.
  8 KB (1,271 words) - 15:04, 20 July 2023
• Audio Visual Speech Separation (1S/1M)
  ...er(s) with the transcript of their respective speech. Lastly, the proposed system must abide by the TinyML[[#ref-reddi2020|&#91;5&#93;]] constraints consider ...en/information/how-to/drawing-schematics.html) or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
  9 KB (1,283 words) - 17:44, 1 September 2023
• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  ...ticast support directly into the interconnect of a shared-memory many-core system called Occamy [4]. In Occamy, 216+1 cores and their tightly-coupled data me ** Develop software to compare the runtime of a reduction with and without your extension
  8 KB (1,177 words) - 11:45, 13 March 2024
• Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
  ...ed.png|450px|thumb|right|The envisioned high-performance multimodal vision system]] ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run
  4 KB (572 words) - 11:07, 5 December 2023
• Design of a Low Power Smart Sensing Multi-modal Vision Platform
  ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run * 60% Software and/or Hardware design
  4 KB (553 words) - 11:02, 5 December 2023
• Object Detection and Tracking on the Edge
  ...s of new possibilities for AI and tinyML. We are creating a completely new system, with an autonomous base station and distributed smart sensor nodes to run * 60% Software and/or Hardware design
  4 KB (523 words) - 10:55, 5 December 2023
• Artificial Reverberation for Embedded Systems
  [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]
  5 KB (578 words) - 12:39, 14 June 2023
• On-Board Software for PULP on a Satellite
  <!-- On-Board Software for PULP on a Satellite (1S) --> ...SAGE CubeSat mission and Trikarenos aims to be onboard, but still requires software both to run its tests in space and interface with the main On-Board Compute
  3 KB (383 words) - 14:29, 18 February 2024
• A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
  ...t needs to be accessed and monitored calls for a high-speed FPGA/GPU based system with a compact, and incubator-compatible hardware design. [[Image:Hangxing FPGA.png|800px| System Overview]]
  6 KB (720 words) - 16:27, 27 September 2023
• Real-time Linux on RISC-V
  ...e that is non-preemptible'' which translates directly into a more reactive system. The core algorithms and data structures that are changed are the timer, in * Propose modifications to Hardware and Software. This will depend on the scope of the thesis (SA or MA). For example, suppo
  3 KB (460 words) - 15:29, 19 February 2024
• Wireless In Action Data Streaming in Ski Jumping (1 B/S)
  ...ta. To improve modern feedback methods in ski jumping, we aim to develop a system that collects athlete performance data with a body-worn sensor node and tra ...with real ski jumpers) shall demonstrate the performance of the developed system. According to the level of the student and the chosen thesis type (BT/ST) t
  6 KB (688 words) - 12:15, 23 July 2023
• Cycle-Accurate Event-Based Simulation of Snitch Core
  ...all, this heterogeneity level requires complex hardware and a full-fledged software stack to evaluate applications while exploiting all platform features. For ''Software Code Style''
  14 KB (2,018 words) - 22:54, 23 November 2023
• Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
  ...l motor control during action is difficult. Therefore, we aim to develop a system that translates sensor data into simple, motor-transferable information onl [[Category:System on Chips for IoTs]]
  6 KB (735 words) - 12:15, 23 July 2023
• Testbed Design for Self-sustainable IoT Sensors
  * 70% Software and hardware design ...ng Projects]] [[Category:EmbeddedAI]] [[Category:SmartSensors]] [[Category:System Design]] [[Category:2023]] [[Category:Semester Thesis]] [[Category:Bachelor
  3 KB (356 words) - 13:03, 20 July 2023
• On - Device Continual Learning for Seizure Detection on GAP9
  Epilepsy, a central nervous system disorder, is characterized by abnormal brain activity resulting in seizures ...user without forgetting the properties of prior users who might reuse the system. This necessitates mitigating the "catastrophic forgetting" phenomenon in o
  9 KB (1,326 words) - 11:16, 12 October 2023
• Skin coupling media characterization for fitnesstracker applications (1 B/S)
  * Development of software for testing [[Category:System on Chips for IoTs]]
  5 KB (631 words) - 12:43, 23 July 2023
• Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
  ...(B/S/M), this could be extended to achieve even tighter integration of the system. The these will include some or all of the following tasks: ...zos, they are quite lossy, placing special demands on the electronic drive system. Therefore, characterisation of these transducers is essential for the desi
  7 KB (903 words) - 10:04, 24 July 2023
• Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
  * Development of software for testing [[Category:System on Chips for IoTs]]
  5 KB (631 words) - 10:07, 24 July 2023
• Transformer Deployment on Heterogeneous Many-Core Systems
  ...can efficiently perform self-attention and integrated it into a many-core system called MemPool. ...en/information/how-to/drawing-schematics.html) or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
  6 KB (858 words) - 14:52, 23 October 2023
• Audio Visual Speech Recognition (1S/1M)
  ...er(s) with the transcript of their respective speech. Lastly, the proposed system must abide by the TinyML[[#ref-reddi2020|&#91;5&#93;]] constraints consider ...en/information/how-to/drawing-schematics.html) or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
  9 KB (1,283 words) - 18:08, 1 September 2023
• Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
  ...d efficiency of our RISC-V-based architecture in a 2.5D integrated chiplet system. It is a realization of the Manticore concept architecture presented at the * 30% Bare-metal software development
  6 KB (848 words) - 14:25, 2 May 2024
• RedCap-5G for IOT application on prototype taped-out silicon
  ...of the SoCs is modular and suitable for running a re-scaled version of the software pipeline as well. It is therefore very promising for RedCap applications. ...eline to be run on a scaled-down 16-core version of MemPool: MinPool. This system was taped out in IIS and we are therefore able to do power measurements on
  2 KB (338 words) - 11:31, 23 December 2023
• Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M)
  ...d Spatz on the TeraPool architecture as our hardware platform, a scaled-up system from MemPool [[#ref-Cavalcante2020|&#91;2&#93;]], which has 1024 Snitch cor In this project, you will touch both the software and hardware of vector-based manycore SIMD architecture, creating and execu
  6 KB (844 words) - 11:41, 31 October 2023
• A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
  ...cations in space and we will need your help to optimize and run real-world software on it. * You will implement a software processing pipeline in C on TeraPool, gaining expertise in the implementati
  3 KB (342 words) - 13:02, 12 February 2024
• Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
  ...C standard is designed to retain some backward compatibility with the I²C system, notably allowing designs where existing I²C devices can be connected to a ...ned peripheral into a full SoC system that runs Linux [2]. To this extent, system-level integration, verification and evaluation must be performed as well as
  5 KB (775 words) - 17:17, 18 December 2023
• Efficient collective communications in FlooNoC (1M)
  ...uction support directly into the interconnect of a shared-memory many-core system called Occamy [4]. In Occamy, 216+1 cores and their tightly-coupled data me * '''System integration and evaluation:'''
  6 KB (897 words) - 19:52, 22 February 2024
• Advanced Data Movers for Modern Neural Networks
  # Implement a software driver to leverage the enhanced capabilities of the iDMA * Basic knowledge of and familiarity with the System Verilog language
  3 KB (418 words) - 16:18, 23 November 2023
• GPT on the edge
  [[File:Llama_on_gap9.png|450px|thumb|right|Dreamed System Preview]] * 60% Software design
  4 KB (455 words) - 11:35, 12 March 2024
• On-Device Federated Continual Learning on Nano-Drone Swarms
  ...m in-field evaluation of the FCL algorithm considering a simple, two-drone system. Intermediate evaluation of CL could be beneficial for this task. </p> ...en/information/how-to/drawing-schematics.html) or any other vector drawing software (for block diagrams) is strongly encouraged by the IIS staff.
  10 KB (1,377 words) - 00:49, 29 February 2024
• On-Device Learnable Embeddings for Acoustic Environments
  ...e user’s characteristics can considerably improve the performance of the system[[#ref-Cornell2023|&#91;3&#93;]][[#ref-Cioflan2024|&#91;2&#93;]]. Similarly, ...to only listen to pre-registered users. Our first goal is to devise a KWS system integrating environmental (e.g., speech characteristics, noisy environments
  11 KB (1,500 words) - 01:10, 29 February 2024
• Smart Agriculture System (1-2S)
  [[Category:Software]] In this project, you will develop a smart agriculture system utilizing a sensor platform to optimize irrigation and pest control, aiming
  4 KB (534 words) - 17:09, 16 May 2024
• Air Quality Prediction in Office Rooms (1-2S/M)
  [[Category:Software]] * '''Base Framework for the UTSensorNode:''' Development of a supervisor system to manage the board resources and integrate or develop drivers for differen
  4 KB (490 words) - 17:10, 16 May 2024
• Multi-Modal Environmental Sensing With GAP9 (1-2S)
  [[Category:Software]] ...sing data privacy and security concerns. Thanks to its modular design, the system can be easily tailored to various applications while leveraging the computa
  4 KB (579 words) - 14:14, 16 May 2024
• Sound-Based Vehicle Classification and Counting (1-2S)
  [[Category:Software]] ...nd fine-tuned on a dataset acquired with the device. Besides counting, the system also aims to determine driving direction and speed. On top of this, further
  5 KB (647 words) - 11:24, 14 May 2024
• Spectrometry for Environmental Monitoring (1-2S/M)
  [[Category:Software]] ...ation:''' Optimizations to improve performance and creation of an embedded system integrating the spectrometer with other relevant sensing devices, compatibl
  4 KB (562 words) - 11:34, 14 May 2024
• Structural Health Monitoring (SHM) System (1-2S/M)
  [[Category:Software]] ...egrity. The end goal is to deploy these models into a real-time monitoring system capable of issuing alerts to maintenance teams, thus facilitating prompt an
  3 KB (465 words) - 11:47, 14 May 2024
• Intelligent Disaster Early-Warning System (1-2S/M)
  [[Category:Software]] ...on of your project will be the development of a sophisticated notification system designed to automatically alert both local authorities and the public about
  4 KB (531 words) - 17:09, 16 May 2024