Category:Completed
From iis-projects
These projects have already been completed. You can take a look at the results of the project and learn more.
Digital
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
Nano TCAD
2013
No pages meet these criteria.
Pages in category "Completed"
The following 83 pages are in this category, out of 286 total.
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- Precise Ultra-low-power Timer
- Predictable Execution on GPU Caches
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- PULP-Shield for Autonomous UAV
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULP’s CLIC extensions for fast interrupt handling
- Putting Together What Fits Together - GrÆStl
R
- RazorEDGE: An Evolved EDGE DBB ASIC
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE
- Real-Time ECG Contractions Classification
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex
- Real-Time Optical Flow Using Neural Networks
- Real-Time Stereo to Multiview Conversion
- Real-time View Synthesis using Image Domain Warping
- Reconfigurability of SHA-3 candidates
- Resource Partitioning of Caches
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S)
- Running Rust on PULP
S
- Scattering Networks for Scene Labeling
- SCMI Support for Power Controller Subsystem
- Securing Block Ciphers against SCA and SIFA
- Self-Learning Drones based on Neural Networks
- Semi-Custom Digital VLSI for Processing-in-Memory
- Sensor Fusion for Rockfall Sensor Node
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Shared Correlation Accelerator for an RF SoC
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
- Smart e-glasses for concealed recording of EEG signals
- Smart Meters
- Smart Virtual Memory Sharing
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC
- Spatio-Temporal Video Filtering
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Stand-Alone Edge Computing with GAP8
- Standard Cell Compatible Memory Array Design
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- Streaming Integer Extensions for Snitch (M/1-2S)
- Study and Development of Intelligent Capability for Small-Size UAVs
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things
- Successive Interference Cancellation for 3G Downlink
- Switched Capacitor Based Bandgap-Reference
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
- Synchronisation and Cyclic Prefix Handling For LTE Testbed
- System Analysis and VLSI Design of NB-IoT Baseband Processing
T
- TCNs vs. LSTMs for Embedded Platforms
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
- Time and Frequency Synchronization in LTE Cat-0 Devices
- Time Gain Compensation for Ultrasound Imaging
- Timing Channel Mitigations for RISC-V Cores
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
- Toward Superposition of Brain-Computer Interface Models
- Towards Autonomous Navigation for Nano-Blimps
- Towards Self-Sustainable Unmanned Aerial Vehicles
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Trace Debugger for custom RISC-V Core
- Transformer Deployment on Heterogeneous Many-Core Systems
- Transforming MemPool into a CGRA (M)
- Triple-Core PULPissimo
- Turbo Decoder Design for High Code Rates
- Turbo Equalization for Cellular IoT
U
- Ultra low power wearable ultrasound probe
- Ultra Low-Power Oscillator
- Ultra-low power processor design
- Ultra-low power sampling front-end for acquisition of physiological signals
- Ultra-low power transceiver for implantable devices
- Ultrafast Medical Ultrasound imaging on a GPU
- Ultrasound based hand gesture recognition
- Ultrasound Doppler system development
- Ultrasound Low power WiFi with IMX7
- Ultrasound signal processing acceleration with CUDA
- Ultrasound-EMG combined hand gesture recognition
