Category:Master Thesis
From iis-projects
The projects listed here are Master thesis projects. In principle a master project at IIS can take no longer than 6 months, and the student is expected to work full time on the thesis project. In some cases it is possible to make a simplified version of the project as a semester thesis, talk to the supervisor of the project to discuss this possibility.
Pages in category "Master Thesis"
The following 52 pages are in this category, out of 424 total.
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- A computational memory unit using phase-change memory devices
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
- A Multiview Synthesis Core in 65 nm CMOS
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- A Unified Compute Kernel Library for Snitch (1-2S)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- A Wearable System To Control Phone And Electronic Device Without Hands
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- A Wireless Sensor Network for a Smart Building Monitor and Control
- A Wireless Sensor Network for a Smart LED Lighting control
- A Wireless Sensor Network for HPC monitoring
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Accelerator for Boosted Binary Features
- Accelerator for Spatio-Temporal Video Filtering
- Accurate deep learning inference using computational memory
- Active-Set QP Solver on FPGA
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Advanced 5G Repetition Combining
- Advanced EEG glasses
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Ambient RF Energy harvesting for Wireless Sensor Network
- AMZ Driverless Competition Embedded Systems Projects
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
- An Efficient Compiler Backend for Snitch (1S/B)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- An Industrial-grade Bluetooth LE Mesh Network Solution
- An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Analog building blocks for mmWave manipulation
- Analog Compute-in-Memory Accelerator Interface and Integration
- Android reliability governor
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
- ASIC Design of a Gaussian Message Passing Processor
- ASIC Design of a Sigma Point Processor
- ASIC Development of 5G-NR LDPC Decoder
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- ASR-Waveformer
- Audio Video Preprocessing In Parallel Ultra Low Power Platform
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning