User contributions
From iis-projects
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- 10:14, 29 August 2023 (diff | hist) . . (+2,934) . . N Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M) (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:FPGA Category:2023 Category:Master Thesis Category:Tbenz ...")
- 09:46, 29 August 2023 (diff | hist) . . (+1,620) . . N Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (Created page with "<!-- Creating Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:C...")
- 09:31, 29 August 2023 (diff | hist) . . (+1) . . Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (current)
- 09:31, 29 August 2023 (diff | hist) . . (+1) . . A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- 09:31, 29 August 2023 (diff | hist) . . (-2) . . Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- 09:49, 5 January 2023 (diff | hist) . . (-1) . . m A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- 09:48, 5 January 2023 (diff | hist) . . (-1) . . m Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
- 08:07, 8 November 2022 (diff | hist) . . (+2,089) . . N Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (Created page with "<!-- Creating Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture [...")
- 07:52, 8 November 2022 (diff | hist) . . (0) . . Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- 07:51, 8 November 2022 (diff | hist) . . (-9) . . Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- 07:46, 8 November 2022 (diff | hist) . . (+1,417) . . N Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) (Created page with "<!-- Creating Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architect...")
- 12:55, 7 November 2022 (diff | hist) . . (+1,794) . . N Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (Created page with "<!-- Creating Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture...")
- 11:56, 7 November 2022 (diff | hist) . . (+1,776) . . N Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (Created page with "<!-- Creating Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:...")
- 11:44, 7 November 2022 (diff | hist) . . (+1,705) . . N Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) (Created page with "<!-- Creating Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) --> Category:Di...")
- 11:27, 7 November 2022 (diff | hist) . . (-8) . . Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- 11:25, 7 November 2022 (diff | hist) . . (+2,184) . . N Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (Created page with "<!-- Creating Towards a High-performance Open-source Verification Suite for AXI-based Systems (1-3S/B) --> Category:Digital Category:High Performance SoCs Category:...")
- 10:52, 7 November 2022 (diff | hist) . . (+3) . . Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- 10:51, 7 November 2022 (diff | hist) . . (+3) . . Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- 10:51, 7 November 2022 (diff | hist) . . (0) . . Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
- 10:51, 7 November 2022 (diff | hist) . . (+2) . . Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
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