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Showing below up to 100 results in range #501 to #600.
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- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (7 revisions)
- Ibex: FPGA Optimizations (7 revisions)
- Digital Audio Interface for Smart Intensive Computing Triggering (7 revisions)
- Ultrasound Low power WiFi with IMX7 (7 revisions)
- Indoor Positioning with Bluetooth (7 revisions)
- Efficient NB-IoT Uplink Design (7 revisions)
- Development of a Rockfall Sensor Node (7 revisions)
- Digital Audio Processor for Cellular Applications (7 revisions)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (7 revisions)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (7 revisions)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (7 revisions)
- Efficient Search Design for Hyperdimensional Computing (7 revisions)
- RazorEDGE: An Evolved EDGE DBB ASIC (7 revisions)
- Transforming MemPool into a CGRA (M) (7 revisions)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (7 revisions)
- Spiking Neural Network for Autonomous Navigation (7 revisions)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (7 revisions)
- Zephyr RTOS on PULP (7 revisions)
- EEG artifact detection for epilepsy monitoring (7 revisions)
- Fault Tolerance (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- LTE IoT Network Synchronization (7 revisions)
- Characterization techniques for silicon photonics-Lumiphase (7 revisions)
- Physical Implementation of ITA (2S) (8 revisions)
- Weekly Reports (8 revisions)
- Streaming Layer Normalization in ITA (M/1-2S) (8 revisions)
- OTDOA Positioning for LTE Cat-M (8 revisions)
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S) (8 revisions)
- EvalEDGE: A 2G Cellular Transceiver FMC (8 revisions)
- Resource Partitioning of RPC DRAM (8 revisions)
- A Unified Compute Kernel Library for Snitch (1-2S) (8 revisions)
- Extend the RI5CY core with priviledge extensions (8 revisions)
- Object Detection and Tracking on the Edge (8 revisions)
- Hardware Accelerator Integration into Embedded Linux (8 revisions)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (8 revisions)
- NVDLA meets PULP (8 revisions)
- Implementation of a Cache Reliability Mechanism (1S/M) (8 revisions)
- Evaluating SoA Post-Training Quantization Algorithms (8 revisions)
- (M/1-2S): A Snitch-based Compute Accelerator for HERO (8 revisions - redirect page)
- Sandro Belfanti (8 revisions)
- Analog Compute-in-Memory Accelerator Interface and Integration (8 revisions)
- Learning at the Edge with Hardware-Aware Algorithms (8 revisions)
- Semi-Custom Digital VLSI for Processing-in-Memory (8 revisions)
- Wireless EEG Acquisition and Processing (8 revisions)
- Investigation of Metal Diffusion in Oxides for CBRAM Applications (8 revisions)
- Machine Learning on Ultrasound Images (8 revisions)
- ISA extensions in the Snitch Processor for Signal Processing (M) (8 revisions)
- An FPGA-Based Evaluation Platform for Mobile Communications (8 revisions)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (8 revisions)
- Flexible Electronic Systems and Epidermal Devices (8 revisions - redirect page)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (8 revisions)
- Pirmin Vogel (8 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (8 revisions)
- Implementing Hibernation on the ARM Cortex M0 (8 revisions)
- Evaluating the RiscV Architecture (8 revisions)
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC (8 revisions)
- BCI-controlled Drone (8 revisions)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (8 revisions)
- Manycore System on FPGA (M/S/G) (8 revisions)
- Fast Wakeup From Deep Sleep State (8 revisions)
- Multi issue OoO Ariane Backend (M) (8 revisions)
- PREM Runtime Scheduling Policies (8 revisions)
- Hypervisor Extension for Ariane (M) (8 revisions)
- Deep Convolutional Autoencoder for iEEG Signals (8 revisions)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (8 revisions)
- ASIC Implementation of Jammer Mitigation (8 revisions)
- Development of a fingertip blood pressure sensor (8 revisions)
- Hardware/software co-programming on the Parallella platform (8 revisions)
- Ultra Low-Power Oscillator (8 revisions)
- Modular Distributed Data Collection Platform (8 revisions)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (8 revisions)
- SCMI Support for Power Controller Subsystem (8 revisions)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (8 revisions)
- Fault-Tolerant Floating-Point Units (M) (8 revisions)
- ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format (8 revisions)
- Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) (8 revisions)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (8 revisions)
- A Trustworthy Three-Factor Authentication System (8 revisions)
- A computational memory unit using phase-change memory devices (8 revisions)
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication (9 revisions)
- Gomeza old project4 (9 revisions)
- Real-time eye movement analysis on a tablet computer (9 revisions)
- Minimal Cost RISC-V core (9 revisions)
- Next Generation Synchronization Signals (9 revisions)
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration (9 revisions)
- Feature Extraction for Speech Recognition (1S) (9 revisions)
- Machine Learning for extracting Muscle features using Ultrasound 2 (9 revisions)
- Karim Badawi (9 revisions)
- Design and Implementation of an Approximate Floating Point Unit (9 revisions)
- Ultrasound-EMG combined hand gesture recognition (9 revisions)
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces (9 revisions)
- Hyper-Dimensional Computing Based Predictive Maintenance (9 revisions)
- Efficient Implementation of an Active-Set QP Solver for FPGAs (9 revisions)
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning (9 revisions)
- Knowledge Distillation for Embedded Machine Learning (9 revisions)
- HERO: TLB Invalidation (9 revisions)
- Hyper Meccano: Acceleration of Hyperdimensional Computing (9 revisions)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication (9 revisions)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (9 revisions)
- Time and Frequency Synchronization in LTE Cat-0 Devices (9 revisions)
