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• Main Page
  * [[Analog| Analog and Mixed Signal Design]] * [[Digital| Digital Circuits and Systems]]
  5 KB (540 words) - 12:31, 8 May 2024
• Ultra-low power processor design
  [[File:Ultra-low power processor design.jpg|thumb]] : 50% ASIC Design
  10 KB (1,669 words) - 19:01, 30 January 2014
• Template
  : 40% ASIC Design * '''[[Design Review]]'''
  4 KB (397 words) - 15:44, 14 February 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  ...rization and testing of piezoelectric polymers. It also aims to design the digital architecture in such a way that later studies will allow '''ML-based contro The development of a digital architecture that enables ML-based control of polarization and testing can
  6 KB (741 words) - 18:14, 21 July 2023
• Digital Transmitter for Mobile Communications
  ...applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an ana ...finally measured during the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can b
  3 KB (382 words) - 20:00, 26 September 2017
• Putting Together What Fits Together - GrÆStl
  [[File:Graestl.png|thumb|500px|Top: FPGA floorplan containing the microprocessor and the ing a separate AES/Grøstl design and GrÆStl.]]
  3 KB (434 words) - 12:01, 26 March 2015
• Digitally-Controlled Analog Subtractive Sound Synthesis
  ...(short for Musical Instrument Digital Interface) using a Raspberry Pi and digital-to-analog converters (DACs). The student(s) will first familiarize themselv : PCB design experience
  5 KB (597 words) - 12:56, 4 December 2021
• Accelerator for Spatio-Temporal Video Filtering
  : 70% Hw Architecture & ASIC Implementation * '''[[Design Review]]'''
  3 KB (366 words) - 12:40, 1 June 2017
• Accelerator for Boosted Binary Features
  ...([[Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment]]), : 40% Hw Architecture & FPGA Implementation
  3 KB (373 words) - 11:51, 19 August 2017
• Sandro Belfanti
  * Digital design * Digital signal processing
  2 KB (336 words) - 17:27, 1 November 2017
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  ...IBM TrueNorth architecture [Merolla14], an homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification at a very low po Tight integration of digital spiking neurons with other kinds of low-power computers is a totally unexpl
  5 KB (784 words) - 14:50, 30 November 2016
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  ...throughputs of 100Gbit/s and even more, either as an ASIC or as part of an FPGA project. You will compare your personal results with previous work from oth * Attend VLSI II (for ASIC designs)
  2 KB (317 words) - 13:13, 14 April 2016
• Indoor Positioning with Bluetooth
  The goal of this project is to implement the digital baseband of a Bluetooth LE receiver, that is able to gather information abo : 50% Hardware design (HLS or VHDL)
  3 KB (449 words) - 12:12, 4 November 2019
• Advanced 5G Repetition Combining
  ...IC with only this block, or integrate it into our RF SoC and test it on an FPGA. : 40% Hardware Design (HLS/VHDL)
  3 KB (345 words) - 10:52, 5 April 2022
• Hardware Accelerator for Model Predictive Controller
  : 40% ASIC Design * '''[[Design Review]]'''
  3 KB (456 words) - 08:35, 20 January 2021
• Digital Beamforming for Ultrasound Imaging
  ...table 3D ultrasound systems, new algorithms and hardware architectures for digital beamforming are currently being developed at IIS. ...feasibility study of the complete beamformer architecture, the fabricated ASIC is tested, measured and physically characterized in a second phase.
  3 KB (423 words) - 11:23, 10 November 2017
• Digital Transmitter for Cellular IoT
  ...ill involve modeling in Matlab but mostly it is HDL design, synthesis, and FPGA testing. This project is a perfect opportunity to apply architectural design methods. The outcome is likely to be the first EC-GSM capable transmitter i
  3 KB (384 words) - 16:41, 17 July 2016
• Design of an LTE Module for the Internet of Things
  ...a hardware description language (HDL) and deploy it to the LTE transceiver FPGA board. : 50% FPGA Design
  3 KB (335 words) - 14:20, 4 November 2019
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
  # The power dissipation of a digital circuit is proportional to the squared supply voltage. Reducing it to the l ...ion should also serve as evaluation platform for a later mixed-signal ASIC design.
  3 KB (438 words) - 18:06, 3 February 2015
• Real-Time Optical Flow Using Neural Networks
  [[Category:Digital]] [[Category:Software]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Digital]] [[Category:System Design]]
  5 KB (707 words) - 11:22, 5 February 2016
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
  In this project you will develop and FPGA-based testbed for the 3G standard TD-SCDMA, with the option to extend it with an ASIC in the
  1 KB (169 words) - 16:42, 9 December 2015
• Vector Processor for In-Memory Computing
  : Interest in processor design : 40% Architecture Design & Exploration
  3 KB (443 words) - 13:10, 2 November 2015
• FFT-based Convolutional Network Accelerator
  ...The focus of this work is on speeding up this step by creating an ASIC or FPGA accelerator to perform this step faster and more power-efficiently in the f [[Category:Digital]] [[Category:FPGA]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2015]]
  8 KB (1,145 words) - 11:30, 5 February 2016
• High-speed Scene Labeling on FPGA
  ...and a display or an ethernet adapter. As opposed to an ASIC project, such FPGA and hardware-software codesign work is much more applicable in industry and [[Category:Digital]] [[Category:FPGA]] [[Category:Completed]] [[Category:2016]] [[Category:Semester Thesis]]
  8 KB (1,197 words) - 18:18, 29 August 2016
• Michael Muehlberghuber
  * Digital design, design flows, ASIC design * ASIC and FPGA design of cryptographic hardware
  1 KB (139 words) - 12:39, 7 November 2017
• Time Synchronization for 3G Mobile Communications
  ...er working with FPGAs, you can alternatively implement the algorithm on an FPGA and test it in real-time and with real data on our 3G testbed. [[Category:Digital]]
  3 KB (420 words) - 11:22, 14 April 2016
• Spatio-Temporal Video Filtering
  * '''[[Design Review]]''' ...esis]] [[Category:Hot]] [[Category:Completed]][[Category:ASIC]] [[Category:FPGA]] [[Category:2016]]
  3 KB (373 words) - 19:40, 14 April 2016
• Switched Capacitor Based Bandgap-Reference
  ...re important building blocks in analog and mixed-signal integrated circuit design. The classical Band Gap-Reference combines the negative VBE temperature coe ...is offers the possibility to study main aspects of analog and mixed-signal design, such as noise, linearity, matching, small signal-concepts and power consum
  4 KB (471 words) - 11:13, 3 May 2018
• Compressed Sensing vs JPEG
  ...le step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very li ...al ASIC (Application Specific Integrated Circuit) or the implementation in FPGA (Field-Programmable Gate Array).
  2 KB (343 words) - 10:24, 14 September 2016
• Compressed Sensing for Wireless Biosignal Monitoring
  ...le step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very li ...V4.0_Homer.html] including analog front-end, analog-to-digital conversion, digital signal processing and a compressed sensing encoder stage.
  2 KB (353 words) - 08:35, 20 January 2021
• Improving our Smart Camera System
  [[Category:Digital]] [[Category:System]] [[Category:Semester Thesis]] [[Category:Group Work]] * for the student(s) to get to know the FPGA design flow from specification through architecture exploration to implementation,
  8 KB (1,176 words) - 16:26, 30 October 2020
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  [[File:origami-fpga-system.png|400px|thumb]] ...e Origami accelerator to run efficiently on the FPGA, hardware/software-co-design configuring memory and DMA controllers, building small IP cores to finish t
  3 KB (397 words) - 18:17, 29 August 2016
• Internet of Things Network Synchronizer
  ...he [[stoneEDGE]] project and the [[evalEDGE]] RF board. Synthesis and ASIC design are also an option. [[Category:Digital]]
  4 KB (582 words) - 20:00, 26 September 2017
• Rethinking our Convolutional Network Accelerator Architecture
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Not available]] [[Category:Semester Thesis]] [[Category:Master ...hitecture exploration to implementation, functional verification, back-end design and silicon testing.
  9 KB (1,263 words) - 18:52, 12 December 2016
• Non-binary LDPC Decoder for Deep-Space Optical Communications
  ...master project the complete decoder could be implemented and tested on an FPGA. : 30% RTL Design
  2 KB (290 words) - 16:05, 21 July 2016
• Turbo Equalization for Cellular IoT
  ...hm to an HDL implementation and synthesize it either towards an FPGA or an ASIC implementation in order to analyze the hardware complexity of the developed * '''[[Design Review]]'''
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [4] capable of implementing PULP [5] with 4 to 8 clusters and a total of 32 ...mplementation on the Xilinx Virtex-7 FPGA but if desired, an ASIC back-end design can also be implemented.
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  ...developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decode : 30% Architectural Design
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  ...developed RTL code. The work concludes with a comparison of the generated ASIC with literature and especially with implementations of other channel decode : 30% Architectural Design
  3 KB (418 words) - 14:01, 13 November 2020
• Bringing XNOR-nets (ConvNets) to Silicon
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016]] ...hitecture exploration to implementation, functional verification, back-end design and silicon testing.
  10 KB (1,357 words) - 16:25, 30 October 2020
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  1. design a low-power interface in standard cell technology that could be used to lin ...the cochleaLP sensor. In this target, the interface resides on a low-power FPGA (e.g. an a MicroSemi IGLOO).
  9 KB (1,427 words) - 18:36, 5 September 2019
• LightProbe
  ...hardware (phone, tablet, workstation) for post-processing over a standard digital link as simple as a standard peripheral, like a camera. * Implementation of processing subunits: Hardware design FPGA/ASIC (VHDL/HLS)
  2 KB (254 words) - 14:14, 31 October 2020
• Single-Bit-Synapse Spiking Neural System-on-Chip
  ...IBM TrueNorth architecture [Merolla14], a homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification at a very low po ...omize and use this neuron to create a scalable spiking neuron for FPGA and ASIC targets. Whereas that work marked a starting point for the development of a
  7 KB (1,000 words) - 12:22, 13 January 2017
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  [[Category:Software]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016] Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the rel
  6 KB (823 words) - 08:36, 20 January 2021
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  : 40% Architecture Design * '''[[Design Review]]'''
  4 KB (467 words) - 13:38, 10 November 2020
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016]] ...ccess which can be exploited by an application-specific integrated circuit ASIC, in contrast to CPUs or even GPUs.
  6 KB (842 words) - 08:37, 20 January 2021
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...ly quantized CNNs (''YodaNN'' [Andri2017]), in the Ergo project we want to design a PULP-based entire computation cluster around a set of deep, fast and low- ...er the QNE should be an extension to the currently existing XNE or a novel design based on the same building blocks.
  6 KB (949 words) - 13:41, 10 November 2020
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  * AER-SPI interface, implemented on an ULP FPGA development board (see [http://iis-projects.ee.ethz.ch/index.php/Interfacin AER-SPI interface is a custom IP hosted on an ULP FPGA development board. It efficiently collects and stores the data produced asy
  7 KB (1,025 words) - 19:52, 30 May 2017
• A computational memory unit using phase-change memory devices
  ...t. The ideal candidate should be well versed in digital and analog circuit design with hands on experimental experience. A strong mathematical background and : Basics of Digital and Analog Design (VLSI1/AIC)
  4 KB (546 words) - 11:33, 17 April 2020
• Deep Learning for Brain-Computer Interface
  [[Category:Digital]] [[Category:FPGA]]
  3 KB (372 words) - 20:22, 1 April 2019

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