Category:Digital
From iis-projects
Projects that are part of the Digital Circuits and Systems group
Active Projects
These are the projects that are currently active
- Real-time Linux on RISC-V
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S)
- Developing a small portable neutron detector for detecting smuggled nuclear material
Available Projects
We are still looking for students/partners to work on the following projects
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- On-Device Learnable Embeddings for Acoustic Environments
- On-Device Federated Continual Learning on Nano-Drone Swarms
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extreme-Edge Experience Replay for Keyword Spotting
- Low Precision Ara for ML
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- FPGA mapping of RPC DRAM
- GPT on the edge
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets
- Modeling FlooNoC in GVSoC (S/M)
- Advanced Data Movers for Modern Neural Networks
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)
- EEG-based drowsiness detection
- In-ear EEG signal acquisition
- EEG earbud
- NeuroSoC RISC-V Component (M/1-2S)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Realtime Gaze Tracking on Siracusa
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings
- System Emulation for AR and VR devices
- Learning at the Edge with Hardware-Aware Algorithms
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Advanced EEG glasses
- Softmax for Transformers (M/1-2S)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Testbed Design for Self-sustainable IoT Sensors
- Towards Flexible and Printable Wearables
- Modular Distributed Data Collection Platform
- Cycle-Accurate Event-Based Simulation of Snitch Core
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S)
- A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
- Object Detection and Tracking on the Edge
- Design of a Low Power Smart Sensing Multi-modal Vision Platform
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems
- Energy Efficient AXI Interface to Serial Link Physical Layer
- Energy Efficient Serial Link
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- BirdGuard
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Audio Visual Speech Separation and Recognition (1S/1M)
- Predict eye movement through brain activity
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Resource Partitioning of RPC DRAM
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)
- All the flavours of FFT on MemPool (1-2S/B)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Ultrasound image data recycler
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- Extended Verification for Ara
- Design of combined Ultrasound and PPG systems
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- An Efficient Compiler Backend for Snitch (1S/B)
- PULP Freertos with LLVM
- Integration Of A Smart Vision System
- Towards Formal Verification of the iDMA Engine (1-3S/B)
- Event-based navigation on autonomous nano-drones
- Improving datarate and efficiency of ultra low power wearable ultrasound
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
- Battery indifferent wearable Ultrasound
- Wearable Ultrasound for Artery monitoring
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Improved Collision Avoidance for Nano-drones
- Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
- Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
- Deep Learning-based Global Local Planner for Autonomous Nano-drones
- Ultra-wideband Concurrent Ranging
- Enhancing our DMA Engine with Fault Tolerance
- Fast Accelerator Context Switch for PULP
- Visualization of Neural Architecture Search Spaces
- Self Aware Epilepsy Monitoring
- Serverless Benchmarks on RISC-V (M)
- Non-blocking Algorithms in Real-Time Operating Systems
- EEG artifact detection with machine learning
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- EEG artifact detection for epilepsy monitoring
- Fast Simulation of Manycore Systems (1S)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Automatic unplugging detection for Ultrasound probes
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- Huawei Research
- Securing Block Ciphers against SCA and SIFA
- RVfplib
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Short Range Radars For Biomedical Application
- Smart Patch For Heath Care And Rehabilitation
- Autonomus Drones With Novel Sensors And Ultra Wide Band
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Machine Learning on Ultrasound Images
- IP-Based SoC Generation and Configuration (1-3S/B)
- Efficient Search Design for Hyperdimensional Computing
- PREM Runtime Scheduling Policies
- IBM Research
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- BCI-controlled Drone
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Accurate deep learning inference using computational memory
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
- Visualizing Functional Microbubbles using Ultrasound Imaging
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
- Extending the RISCV backend of LLVM to support PULP Extensions
- Compiler Profiling and Optimizing
- PREM Intervals and Loop Tiling
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- PREM on PULP
- Edge Computing for Long-Term Wearable Biomedical Systems
- AMZ Driverless Competition Embedded Systems Projects
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
- Wireless Sensing With Long Range Comminication (LoRa)
- Indoor Smart Tracking of Hospital instrumentation
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
- Physics is looking for PULP
- Embedded Gesture Recognition Using Novel Mini Radar Sensors
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
- An Industrial-grade Bluetooth LE Mesh Network Solution
- BLISS - Battery-Less Identification System for Security
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
- Zero Power Touch Sensor and Reciever For Body Communication
- Wake Up Radio For Energy Efficient Communication System and IC Design
- A Wireless Sensor Network for HPC monitoring
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Power Geolocalization And Indoor Localization
- Real-Time Implementation of Quantum State Identification using an FPGA
- Neural Networks Framwork for Embedded Plattforms
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
- Tiny CNNs for Ultra-Efficient Object Detection on PULP
- Single-Bit-Synapse Spiking Neural System-on-Chip
- OpenRISC SoC for Sensor Applications
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
- PVT Dynamic Adaptation in PULPv3
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
- A Wearable System To Control Phone And Electronic Device Without Hands
- Towards The Integration of E-skin into Prosthetic Devices
- Ultra Low Power Conversion Circuit For Batteryless Applications
- Towards Self Sustainable UAVs
- Using Motion Sensors to Support Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Bateryless Heart Rate Monitoring
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
- Covariant Feature Detector on Parallel Ultra Low Power Architecture
- Ultra-Efficient Visual Classification on Movidius Myriad2
- Kinetic Energy Harvesting For Autonomous Smart Watches
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
- Autonomous Smart Watches: Hardware and Software Desing
- A Wireless Sensor Network for a Smart LED Lighting control
- Compressed Sensing vs JPEG
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
- Real-Time Pedestrian Detection For Privacy Enhancement
- Thermal Control of Mobile Devices
- Android reliability governor
- Infrared Wake Up Radio
- Ambient RF Energy harvesting for Wireless Sensor Network
- Hardware Support for IDE in Multicore Environment
- Audio DAC Conversion Jitter Measurement System
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
- Ultra Low Power Wake Up Radio for Wireless Sensor Network
- Variability Tolerant Ultra Low Power Cluster
Completed Projects
These are projects that were completed in the last few years
2013
- RazorEDGE: An Evolved EDGE DBB ASIC
- Real-Time Stereo to Multiview Conversion
- NORX - an AEAD algorithm for the CAESAR competition
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- SHAre - An application Specific Instruction Set Processor for SHA-2/3
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- Real-time View Synthesis using Image Domain Warping
- Ultra-low power processor design
2012
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
2011
- Compressed Sensing Reconstruction on FPGA
- A Multiview Synthesis Core in 65 nm CMOS
- Real-time View Synthesis using Image Domain Warping
- Putting Together What Fits Together - GrÆStl
Pages in category "Digital"
The following 200 pages are in this category, out of 607 total.
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- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
- EvalEDGE: A 2G Cellular Transceiver FMC
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
- Evaluating An Ultra low Power Vision Node
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- Evaluating SoA Post-Training Quantization Algorithms
- Evaluating the RiscV Architecture
- Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
- Event-based navigation on autonomous nano-drones
- Event-Driven Convolutional Neural Network Modular Accelerator
- Event-Driven Vision on an embedded platform
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
- Exploring Algorithms for Early Seizure Detection
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
- Exploring NAS spaces with C-BRED
- Exploring schedules for incremental and annealing quantization algorithms
- Extend the RI5CY core with priviledge extensions
- Extended Verification for Ara
- Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Extending our FPU with Internal High-Precision Accumulation (M)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Extending the RISCV backend of LLVM to support PULP Extensions
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Extreme-Edge Experience Replay for Keyword Spotting
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
F
- Fabian Schuiki
- Fast Accelerator Context Switch for PULP
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
- Fast Simulation of Manycore Systems (1S)
- Fast Wakeup From Deep Sleep State
- Fault-Tolerant Floating-Point Units (M)
- Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
- Feature Extraction for Speech Recognition (1S)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
- FFT-based Convolutional Network Accelerator
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
- User:Fischeti
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
- Flexfloat DL Training Framework
- Floating-Point Divide & Square Root Unit for Transprecision
- FPGA mapping of RPC DRAM
- FPGA Optimizations of Dense Binary Hyperdimensional Computing
- FPGA System Design for Computer Vision with Convolutional Neural Networks
- FPGA Testbed Implementation for Bluetooth Indoor Positioning
- FPGA-Based Digital Frontend for 3G Receivers
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
- Frank K. Gürkaynak
- Freedom from Interference in Heterogeneous COTS SoCs
G
H
- Harald Kröll
- Hardware Accelerated Derivative Pricing
- Hardware Accelerator for Model Predictive Controller
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Hardware Constrained Neural Architechture Search
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Hardware Support for IDE in Multicore Environment
- Hardware/software co-programming on the Parallella platform
- Hardware/software codesign neural decoding algorithm for “neural dust”
- HERO: TLB Invalidation
- Heroino: Design of the next CORE-V Microcontroller
- Herschmi
- User:Herschmi
- High Speed FPGA Trigger Logic for Particle Physics Experiments
- High-speed Scene Labeling on FPGA
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers
- High-throughput Embedded System For Neurotechnology in collaboration with INI
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- Huawei Research
- Human Intranet
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
- Hyper Meccano: Acceleration of Hyperdimensional Computing
- Hyper-Dimensional Computing Based Predictive Maintenance
- Hypervisor Extension for Ariane (M)
I
- Ibex: Bit-Manipulation Extension
- Ibex: FPGA Optimizations
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- IBM Research
- Image and Video Processing
- Image Sensor Interface and Pre-processing
- Implementation of a Cache Reliability Mechanism (1S/M)
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Implementation of a NB-IoT Positioning System
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Implementation of an Accelerator for Retentive Networks (1-2S)
- Implementation of an AES Hardware Processing Engine (B/S)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- Implementing A Low-Power Sensor Node Network
- Implementing Configurable Dual-Core Redundancy
- Implementing DSP Instructions in Banshee (1S)
- Implementing Hibernation on the ARM Cortex M0
- Improved Collision Avoidance for Nano-drones
- Improved Reacquisition for the 5G Cellular IoT
- Improved State Estimation on PULP-based Nano-UAVs
- Improving Cold-Start in Batteryless And Energy Harvesting Systems
- Improving datarate and efficiency of ultra low power wearable ultrasound
- Improving our Smart Camera System
- Improving Resiliency of Hyperdimensional Computing
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
- In-ear EEG signal acquisition
- Indoor Positioning with Bluetooth
- Indoor Smart Tracking of Hospital instrumentation
- Infrared Wake Up Radio
- Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
- Integrating Hardware Accelerators into Snitch (1S)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
- Integration Of A Smart Vision System
- Intelligent Power Management Unit (iPMU)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
- Interference Cancellation for EC-GSM-IoT
- Internet of Things Network Synchronizer
- Internet of Things SoC Characterization
- Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
- Investigation of Quantization Strategies for Retentive Networks (1S)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- IoT Turbo Decoder
- IP-Based SoC Generation and Configuration (1-3S/B)
- ISA extensions in the Snitch Processor for Signal Processing (M)
K
L
- User:Lbertaccini
- Learning at the Edge with Hardware-Aware Algorithms
- Learning Image Compression with Convolutional Networks
- Learning Image Decompression with Convolutional Networks
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Libria
- LightProbe
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
- LightProbe - CNN-Based-Image-Reconstruction
- LightProbe - Design of a High-Speed Optical Link
- LightProbe - Frontend Firmware and Control Side Channel
- LightProbe - Implementation of compressed-sensing algorithms
- LightProbe - Thermal-Power aware on-head Beamforming
- LightProbe - Ultracompact Power Supply PCB
- LightProbe - WIFI extension (PCB)
- LLVM and DaCe for Snitch (1-2S)
- Low Latency Brain-Machine Interfaces
- Low Power Geolocalization And Indoor Localization
- Low Power Neural Network For Multi Sensors Wearable Devices
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
- Low Precision Ara for ML
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Low-power Clock Generation Solutions for 65nm Technology
- LTE IoT Network Synchronization
- User:Lukasc
M
- Machine Learning for extracting Muscle features from Ultrasound raw data
- Machine Learning for extracting Muscle features using Ultrasound
- Machine Learning for extracting Muscle features using Ultrasound 2
- Machine Learning on Ultrasound Images
- User:Mandrea
- Manycore System on FPGA (M/S/G)
- Mapping Networks on Reconfigurable Binary Engine Accelerator
- Matheus Cavalcante
- User:Matheusd
- Matthias Korb
- Mauro Salomon
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- User:Meggiman
- Memory Augmented Neural Networks in Brain-Computer Interfaces
- MemPool on HERO (1S)
- Minimal Cost RISC-V core
- Minimum Variance Beamforming for Wearable Ultrasound Probes
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
- User:Mmaxim
- Modeling FlooNoC in GVSoC (S/M)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
- Modular Distributed Data Collection Platform
- Monocular Vision-based Object Following on Nano-size Robotic Blimp
- Moritz Schneider
- Multi issue OoO Ariane Backend (M)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA
N
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
- Network-off-Chip (M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
- Neural Networks Framwork for Embedded Plattforms
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
- NeuroSoC RISC-V Component (M/1-2S)
- New RVV 1.0 Vector Instructions for Ara
- Next Generation Channel Decoder
- Next Generation Synchronization Signals
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
- Non-binary LDPC Decoder for Deep-Space Optical Communications
- Non-blocking Algorithms in Real-Time Operating Systems
- Norbert Felber
- NORX - an AEAD algorithm for the CAESAR competition